SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, 3/e (Paperback)
Chris Spear, Greg Tumbush
- 出版商: Springer
- 出版日期: 2014-04-13
- 售價: $2,930
- 貴賓價: 9.5 折 $2,784
- 語言: 英文
- 頁數: 508
- 裝訂: Paperback
- ISBN: 1489995005
- ISBN-13: 9781489995001
-
相關分類:
Verilog
-
相關翻譯:
System Verilog 驗證：測試平臺編寫指南, 3/e (SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, 3/e) (簡中版)
-
其他版本:
Systemverilog for Verification: A Guide to Learning the Testbench Language Features, 3/e (Hardcover)
買這商品的人也買了...
-
Verilog 硬體描述語言 (Verilog HDL: A Guide to Digital Design and Synthesis, 2/e)$480$432 -
Integrated Circuit Design, 4/e (IE-Paperback)$1,580$1,568 -
Intermediate Perl, 2/e (Paperback)$1,496$1,418 -
Advanced Chip Design, Practical Examples in Verilog (Paperback)$1,760$1,672 -
The Uvm Primer: A Step-By-Step Introduction to the Universal Verification Methodology (Paperback)$1,930$1,834 -
Getting Started with UVM: A Beginner's Guide (Paperback)$1,130$1,074 -
$281SystemVerilog 驗證 -
$1,615Cracking the Coding Interview : 189 Programming Questions and Solutions, 6/e (Paperback) -
精通 Python｜運用簡單的套件進行現代運算 (Introducing Python: Modern Computing in Simple Packages)$780$616 -
Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)$4,410$4,190 -
$250Vivado 從此開始 -
Linux Shell 程式設計與管理實務, 3/e$690$538 -
精通 Shell 程式設計, 4/e (Shell Programming in Unix, Linux and OS X: The Fourth Edition of Unix Shell Programming, 4/e)$580$458 -
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design (Paperback)$4,230$4,019 -
$267深入淺出 SSD：固態存儲核心技術、原理與實戰 -
芯片驗證漫游指南 : 從系統理論到 UVM 的驗證全視界$594$564 -
MIS 一定要懂的 82個伺服器建置與管理知識$420$332 -
Python：股票演算法交易實務 145個關鍵技巧詳解$500$390 -
Verilog 編程藝術$474$450 -
Perl 學習手冊, 7/e (Learning Perl, 7/e)$680$476 -
Xilinx Zynq-7000 嵌入式系統設計與實現：基於 ArmCortex-A9 雙核處理器和 Vivado 的設計方法, 2/e$1,074$1,020 -
Deep Learning - Hardware Design$680$646 -
Practical UVM: Step by Step with IEEE 1800.2 (Paperback)$2,460$2,337 -
UVM 實戰$474$450 -
A Manual for Writers of Research Papers, Theses, and Dissertations, Ninth Edition: Chicago Style for Students and Researchers$1,260$1,197
相關主題
商品描述
Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.
In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students’ understanding of the material. Other features of this revision include:
- New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard
- Descriptions of UVM features such as factories, the test registry, and the configuration database
- Expanded code samples and explanations
- Numerous samples that have been tested on the major SystemVerilog simulators
SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.
商品描述(中文翻譯)
基於非常成功的第二版，這本擴展版的《SystemVerilog驗證指南：學習測試環境語言特性》教授了SystemVerilog語言的所有驗證特性，並提供了數百個例子來清楚解釋概念和基本原理。它包含了專職驗證工程師和學習這一寶貴技能的學生所需的材料。
在第三版中，作者Chris Spear和Greg Tumbush從如何驗證設計開始，然後利用這個背景來展示語言特性，包括不同風格的優缺點，讓讀者可以在選擇之間做出選擇。這本教科書包含了設計來增強學生對材料的理解的章末練習題。本次修訂的其他特點包括：
- 2009年IEEE語言標準中關於靜態變量、打印格式指定符和DPI的新章節
- UVM特性的描述，如工廠、測試註冊表和配置數據庫
- 擴展的代碼示例和解釋
- 在主要SystemVerilog模擬器上經過測試的大量示例
《SystemVerilog驗證指南：學習測試環境語言特性，第三版》適用於本科或研究生水平的一學期SystemVerilog課程。這個新版的許多改進都是通過數百名讀者提供的反饋來編制的。
