Writing Testbenches: Functional Verification of HDL Models, 2/e (Hardocver)
暫譯: 撰寫測試平台：HDL模型的功能驗證，第2版（精裝本）

Janick Bergeron

Writing Testbenches: Functional Verification of HDL Models, 2/e (Hardocver)

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商品描述

The Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems.

From the Foreword:

Building on the first edition, " ...the most successful and popular contemporary verification textbook", the author raises the verification level of abstraction by introducing coverage-driven constrained random transaction-level self-checking testbenches - all made possible through the introduction of hardware verification languages (HVLs) such as e from Verisity and OpenVera from Synopsys...." Harry Foster, Chief Architect, Verplex Systems, Inc.

Topics included in the new Second Edition:

  • Discussions on OpenVera and e;
  • approaches for writing constrainable random stimulus generators;
  • strategies for making testbenches self-checking;
  • a clear blueprint of a verification process that aims for first time success;
  • recent advances in functional verification such as coverage-driven verification process;
  • VHDL and Verilog language semantics;
  • the semantics are presented in new verification-oriented languages
  • techniques for applying stimulus and monitoring the response of a design;
  • behavioral modeling using non-synthesizeable constructs and coding style;
  • updated for Verilog 2001.

Contents：

About the Cover. Foreword. Preface. Why This Book Is Important. What This Book Is About. What Prior Knowledge You Should Have. Reading Paths. Choosing a Language: VHDL vs. Verilog. Hardware Verification Languages. And the Winner is... For More Information. Acknowledgements.

  • 1: What is Verification? What is a Testbench? The Importance of Verification. Reconvergence Model. The Human Factor. What Is Being Verified? Functional Verification Approaches. Testing Versus Verification. Design and Verification Reuse. The Cost of Verification. Summary.
  • 2: Verification Tools. Linting Tools. Simulators. Verification Intellectual Property. Waveform Viewers. Code Coverage. Functional Coverage. Verification Languages. Assertions. Revision Control. Issue Tracking. Metrics. Summary.
  • 3: The Verification Plan. The Role of the Verification Plan. Levels of Verification. Verification Strategies. From Specification to Features. Directed Testbenches Approach. Coverage-Driven Random-Based Approach. Summary.
  • 4: High-Level Modeling. Behavioral versus RTL Thinking. You Gotta Have Style! Structure of Behavioral Code. Data Abstraction. Object-Oriented Programming. Aspect-Oriented Programming. The Parallel Simulation Engine. Race Conditions. Verilog Portability Issues. Summary.
  • 5: Stimulus and Response. Reference Signals. Simple Stimulus. Simple Output. Complex Stimulus. Bus-Functional Models. Response Monitors. Transaction-Level Interface. Summary.
  • 6: Architecting Testbenches. Test Harness. VHDL Test Harness. Design Configuration. Self-Checking Testbenches. Directed Stimulus. Random Stimulus. Summary.
  • 7: Simulation Management. Behavioral Models. Pass or Fail? Managing Simulations. Regression. Summary.
  • APPENDIX A: Coding Guidelines. Directory Structure. General Coding Guidelines. Naming Guidelines. HDL Coding Guidelines.
  • APPENDIX B: Glossary. Afterwords. Index.

商品描述(中文翻譯)

第二版《撰寫測試平台，HDL模型的功能驗證》介紹了最新的驗證技術，以產生完全功能的第一片矽ASIC、系統單晶片（SoC）、電路板和整個系統。

從前言：
基於第一版，「...當代最成功和受歡迎的驗證教科書」，作者透過引入基於覆蓋的約束隨機交易級自檢測試平台，提升了驗證的抽象層次——這一切都得益於硬體驗證語言（HVLs）的引入，例如Verisity的e和Synopsys的OpenVera....」哈利·福斯特，Verplex Systems, Inc.首席架構師。

新第二版中包含的主題：
- OpenVera和e的討論；
- 撰寫可約束隨機刺激生成器的方法；
- 使測試平台自檢的策略；
- 旨在首次成功的驗證過程的清晰藍圖；
- 最近在功能驗證方面的進展，例如基於覆蓋的驗證過程；
- VHDL和Verilog語言語義；
- 在新的驗證導向語言中呈現語義；
- 應用刺激和監控設計響應的技術；
- 使用不可合成構造和編碼風格的行為建模；
- 更新至Verilog 2001。

內容：
關於封面。前言。序言。為什麼這本書很重要。這本書的內容。您應具備的先前知識。閱讀路徑。選擇語言：VHDL與Verilog。硬體驗證語言。獲勝者是... 更多資訊。致謝。

1: 什麼是驗證？什麼是測試平台？驗證的重要性。重聚模型。人為因素。驗證的對象是什麼？功能驗證方法。測試與驗證。設計和驗證重用。驗證的成本。總結。
2: 驗證工具。Lint工具。模擬器。驗證知識產權。波形查看器。代碼覆蓋率。功能覆蓋率。驗證語言。斷言。版本控制。問題追蹤。度量。總結。
3: 驗證計劃。驗證計劃的角色。驗證層次。驗證策略。從規範到特徵。定向測試平台方法。基於覆蓋的隨機方法。總結。
4: 高階建模。行為思維與RTL思維。你必須有風格！行為代碼的結構。數據抽象。面向對象編程。面向方面編程。並行模擬引擎。競爭條件。Verilog可攜性問題。總結。
5: 刺激與響應。參考信號。簡單刺激。簡單輸出。複雜刺激。總線功能模型。響應監控器。交易級介面。總結。
6: 測試平台的架構。測試工具。VHDL測試工具。設計配置。自檢測試平台。定向刺激。隨機刺激。總結。
7: 模擬管理。行為模型。通過或失敗？管理模擬。回歸。總結。
附錄A：編碼指南。目錄結構。一般編碼指南。命名指南。HDL編碼指南。
附錄B：術語表。後記。索引。

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