Circuit-Technology Co-Optimization of Sram Design in Advanced CMOS Nodes (先進CMOS節點中SRAM設計的電路技術協同優化)
Liu, Hsiao-Hsuan, Catthoor, Francky
相關主題
商品描述
Modern computing engines--CPUs, GPUs, and NPUs--require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes.
The first part of the book utilizes a bottom-up design-technology co-optimization (DTCO) approach, employing a dedicated PPA simulation framework to evaluate and identify the most promising strategies for SRAM bitcell scaling. It offers a comprehensive examination of SRAM bitcell scaling beyond 1 nm node, outlining a structured research cycle that includes identifying scaling bottlenecks, developing cutting-edge architectures with complementary field-effect transistor (CFET) technology, and addressing challenges such as process integration and routing complexities. Additionally, this book introduces a novel write margin methodology to better address the risks of write failures in resistance-dominated nodes. This methodology accounts for time-dependent parasitic bitline effects and incorporates timing setup of write-assist techniques to prevent underestimating the yield loss.
In the second part, the focus shifts to a top-down DTCO approach due to the diminishing returns of bitcell scaling beyond 5 Å node at the macro level. As technology scales, increasing resistance and capacitance (RC) lead designers to adopt smaller subarray sizes to reduce effective RC and enhance subarray-level PPA. However, this approach can result in increased inter-subarray interconnect overhead, potentially offsetting macro-level improvements. This book examines the effects of various subarray sizes on macro-level PPA and finds that larger subarrays can significantly reduce interconnect overhead and improve the energy-delay-area product (EDAP) of SRAM macro. The introduction of the active interconnect (AIC) concept enables the use of larger subarray sizes, while integrating carbon nanotube FET as back-end-of-line compatible devices results in macro-level EDAP improvements of up to 65% when transitioning from standard subarrays to AIC divided subarrays. These findings highlight the future trajectory of SRAM subarray design in deeply scaled nodes.
商品描述(中文翻譯)
現代計算引擎——CPU、GPU 和 NPU——需要大量的 SRAM 來設計快取，這是由於對更高密度、性能和能效的需求不斷增加。本書深入探討超縮放技術節點中的兩個主要領域：(1) 推進 SRAM 位元單元的縮放和 (2) 探索創新的子陣列設計，以提升各技術節點的功率-性能-面積 (PPA) 指標。
本書的第一部分採用自下而上的設計-技術協同優化 (DTCO) 方法，利用專門的 PPA 模擬框架來評估和識別 SRAM 位元單元縮放的最有前景策略。它全面檢視了超過 1 nm 節點的 SRAM 位元單元縮放，概述了一個結構化的研究循環，包括識別縮放瓶頸、開發具有互補場效應晶體管 (CFET) 技術的尖端架構，以及解決如製程整合和佈線複雜性等挑戰。此外，本書引入了一種新穎的寫入裕度方法論，以更好地應對在以電阻為主的節點中寫入失敗的風險。這種方法論考慮了時間依賴的寄生位線效應，並整合了寫入輔助技術的時序設置，以防止低估產量損失。
在第二部分，重點轉向自上而下的 DTCO 方法，因為在宏觀層面上，位元單元縮放超過 5 Å 節點的回報遞減。隨著技術的縮放，增加的電阻和電容 (RC) 使設計師採用更小的子陣列尺寸，以降低有效 RC 並提升子陣列級別的 PPA。然而，這種方法可能導致子陣列間互連開銷的增加，從而抵消宏觀層面的改進。本書檢視了各種子陣列尺寸對宏觀層面 PPA 的影響，發現較大的子陣列可以顯著減少互連開銷，並改善 SRAM 宏觀的能量-延遲-面積乘積 (EDAP)。引入主動互連 (AIC) 概念使得使用更大子陣列尺寸成為可能，而將碳納米管 FET 作為後端兼容設備的整合，則在從標準子陣列過渡到 AIC 分割子陣列時，實現了高達 65% 的宏觀層面 EDAP 改進。這些發現突顯了在深度縮放節點中 SRAM 子陣列設計的未來發展方向。
作者簡介
Hsiao-Hsuan Liu received her Ph.D. degree in Electrical Engineering from KU Leuven, in collaboration with imec, Leuven, Belgium, in 2024. She obtained her M.S. degree from the Graduate Institute of Electronics Engineering at National Taiwan University, Taipei, Taiwan, in 2019, and her B.S. degree in Optics and Photonics from National Central University, Taoyuan, Taiwan, in 2017. Her current research interests include SRAM design and technology co-optimization (DTCO) based on nanosheet (NS), forksheet (FS), and complementary field-effect transistor (CFET) technologies.
Francky Catthoor received a Ph.D. in EE from the Katholieke Univ. Leuven, Belgium in 1987. Between 1987 and 2000, he has headed several research domains in the area of synthesis techniques and architectural methodologies. Since 2000 he is strongly involved in other activities at IMEC including co-exploration of application, computer architecture and deep submicron technology aspects, biomedical systems and IoT sensor nodes, and photo-voltaic modules combined with renewable energy systems, all at IMEC Leuven, Belgium. Currently he is an IMEC senior fellow. He is also part-time full professor at the EE department of the KULeuven. He has been associate editor for several IEEE and ACM journals, and was elected IEEE fellow in 2005.
作者簡介(中文翻譯)
Hsiao-Hsuan Liu於2024年在比利時魯汀的KU Leuven獲得電機工程博士學位，並與imec合作。她於2019年在台灣台北的國立台灣大學電子工程研究所獲得碩士學位，並於2017年在台灣桃園的國立中央大學獲得光學與光子學學士學位。她目前的研究興趣包括基於納米片(nanosheet, NS)、叉片(forksheet, FS)和互補型場效應晶體管(complementary field-effect transistor, CFET)技術的SRAM設計與技術共同優化(DTCO)。
Francky Catthoor於1987年在比利時魯汀的Katholieke Universiteit Leuven獲得電機工程博士學位。在1987年至2000年間，他負責多個合成技術和架構方法論的研究領域。自2000年以來，他積極參與IMEC的其他活動，包括應用、計算機架構和深亞微米技術方面的共同探索、生物醫學系統和物聯網感測器節點，以及與可再生能源系統結合的光伏模組，這些均在IMEC魯汀進行。目前，他是IMEC的高級研究員，同時也是KULeuven電機工程系的兼任教授。他曾擔任多本IEEE和ACM期刊的副編輯，並於2005年被選為IEEE會士。
