Phase Lock Loops and Frequency Synthesis
暫譯: 相位鎖定迴路與頻率合成

Phase lock loop frequency synthesis finds uses in a myriad of wireless applications - from local oscillators for receivers and transmitters to high performance RF test equipment. As the security and reliability of mobile communication transmissions have gained importance, PLL and frequency synthesisers have become increasingly topical subjects.
Phase Lock Loops & Frequency Synthesis examines the various components that make up the phase lock loop design, including oscillators (crystal, voltage controlled), dividers and phase detectors. Interaction amongst the various components are also discussed. Real world problems such as power supply noise, shielding, grounding and isolation are given comprehensive coverage and solved examples with MATHCAD programs are presented throughout.

• Presents a comprehesive study of phase lock loops and frequency synthesis in communication systems
• Written by an internationally-recognised expert in the field
• Details the problem of spurious signals in PLL frequency synthesizers, a topic neglected by available competing titles
• Provides detailed theorectical background coupled with practical examples of state-of-the-art device design
• MATHCAD programs and simulation software to accompany the design exercises and examples

This combination of thorough theoretical treatment and guidance on practical applications will appeal to mobile communication circuit designers and advanced electrical engineering students.

Table of Contents

Preface.

1. Basic Equations of the PLLs.

2. PLLs of the First and Second Order.

3. PLLs of the Third and Higher Orders.

4. Stability of the PLL Systems.

5. Tracking.

6. Working Ranges of PLLs.

7. Acquisition of PLLs.

8. Basic Blocks of PLLs.

9. Noise and Time Jitter.

10. Digital PLLs (Sampled Systems).

11. PLLs in Frequency Synthesis.

12. PLLs and Digital Frequency Synthesizers.

Appendix: List of Symbols.

Index.