Phase-Locking in High-Performance Systems : From Devices to Architectures
暫譯: 高效能系統中的相位鎖定:從裝置到架構
Behzad Razavi
- 出版商: Wiley
- 出版日期: 2003-02-27
- 售價: $7,970
- 貴賓價: 9.5 折 $7,572
- 語言: 英文
- 頁數: 736
- 裝訂: Paperback
- ISBN: 0471447277
- ISBN-13: 9780471447276
海外代購書籍(需單獨結帳)
買這商品的人也買了...
-
$840$798 -
$680$537 -
$299$254 -
$480$379 -
$920$727 -
$880$704 -
$450$351 -
$1,930$1,834 -
$420$328 -
$620$527 -
$750$638 -
$600$588 -
$650$514 -
$760$600 -
$580$493 -
$590$466 -
$480$374 -
$680$537 -
$690$538 -
$420$332 -
$720$562 -
$720$569 -
$750$638 -
$560$476 -
$675LPIC 1 Exam Cram 2: Linux Professional Institute Certification Exams 101 and 102 (Paperback)
商品描述
Comprehensive coverage of recent developments in phase-locked loop technology
The rapid growth of high-speed semiconductor and communication technologies has helped make phase-locked loops (PLLs) an essential part of memories, microprocessors, radio-frequency (RF) transceivers, broadband data communication systems, and other burgeoning fields. Complementing his 1996 Monolithic Phase-Locked Loops and Clock Recovery Circuits (Wiley-IEEE Press), Behzad Razavi now has collected the most important recent writing on PLL into a comprehensive, self-contained look at PLL devices, circuits, and architectures.
Phase-Locking in High-Performance Systems: From Devices to Architectures' five original tutorials and eighty-three key papers provide an eminently readable foundation in phase-locked systems. Analog and digital circuit designers will glean a wide range of practical information from the book's . . .
* Tutorials dealing with devices, delay-locked loops (DLLs), fractional-N synthesizers, bang-bang PLLs, and simulation of phase noise and jitter
* In-depth discussions of passive devices such as inductors, transformers, and varactors
* Papers on the analysis of phase noise and jitter in various types of oscillators
* Concentrated examinations of building blocks, including the design of oscillators, frequency dividers, and phase/frequency detectors
* Articles addressing the problem of clock generation by phase-locking for timing and digital applications, RF synthesis, and the application of phase-locking to clock and data recovery circuits
In tandem with its companion volume, Phase-Locking in High-Performance Systems: From Devices to Architectures is a superb reference for anyone working on, or seeking to better understand, this rapidly-developing and increasingly central technology.
商品描述(中文翻譯)
全面涵蓋相位鎖定迴路技術的最新發展
高速半導體和通信技術的快速增長使得相位鎖定迴路(PLLs)成為記憶體、微處理器、射頻(RF)收發器、寬頻數據通信系統及其他新興領域的重要組成部分。Behzad Razavi 在其1996年的《單片相位鎖定迴路與時鐘恢復電路》(Wiley-IEEE Press)之後,現在將最近有關PLLs的最重要著作彙集成一本全面且自成一體的相位鎖定迴路設備、電路和架構的概述。
《高效能系統中的相位鎖定:從設備到架構》的五篇原創教程和八十三篇關鍵論文為相位鎖定系統提供了極具可讀性的基礎。類比和數位電路設計師將從本書中獲得廣泛的實用資訊,包括:
* 涉及設備、延遲鎖定迴路(DLLs)、分數-N合成器、bang-bang PLLs,以及相位噪聲和抖動模擬的教程
* 對被動元件如電感器、變壓器和可變電容器的深入討論
* 有關各類振盪器的相位噪聲和抖動分析的論文
* 對基本構件的集中檢視,包括振盪器、頻率分頻器和相位/頻率檢測器的設計
* 討論通過相位鎖定生成時鐘以用於定時和數位應用、RF合成,以及相位鎖定在時鐘和數據恢復電路中的應用的文章
與其伴隨的卷冊一起,《高效能系統中的相位鎖定:從設備到架構》是任何從事或希望更好理解這一快速發展且日益重要技術的人的絕佳參考資料。