CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration (Hardcvoer)

Description

CMOS Fractional-N Synthesizers fits in the quest for small and cheap cellular transceiver solutions. The book is conceived as a manual for the design of fully integrated DeltaSigma fractional-N frequency synthesizers in CMOS with a focus on achieving a high spectral purity, i.e. low-phase-noise and high spurious suppression. Fractional-N design is elaborated from specification derivation up to architectural and building block level and down to circuit level.

CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case.

The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques.

On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.

CMOS Fractional-N Synthesizers covers the total design flow of monolithic CMOS fractional-N synthesizers with high spectral purity while providing insight in the most critical issues of monolithic fractional-N synthesis. All material is experimentally verified with several CMOS implementations, with ultimately a monolithic CMOS &Dgr;&Sgr;-controlled fractional-N synthesizer, which was part of a CMOS DCS-1800 transceiver front-end. The book is essential reading for analog and RF design engineers and researchers in the field and it is also suitable as text book for an advanced course on the subject.

 

 

Table of contents

I: Abstract. List of Symbols and Abbreviations.

Table of Contents.

1: Introduction. 1.1. Telecommunications: An Overview. 1.2. Telecommunications: A Market Perception. 1.3. Integration: Why, How and In What? 1.4. The Research Book. 1.5. The Outline of the Book.

2: On Frequency Synthesis. 2.1. Introduction. 2.2. Indirect or Phase-Locked Loop Frequency Synthesizers. 2.3. The Synthesizer Data Sheet. 2.4. Introduction to PLL building blocks. 2.5. Advanced PLL Frequency Synthesizers. 2.6. Frequency Synthesis for the DCS-1800 System. 2.7. Conclusion.

3: High-Speed CMOS Prescalers. 3.1. Introduction. 3.2. The Phase-Switching Dual-Modulus Prescaler. 3.3. A Single-Ended 1.5 GHz 8/9 Dual-Modulus Prescaler in 0.7 mum CMOS. 3.4. A Single-ended 1.8 GHz 8/9 DMP in 0.8 mum "Radiation Hardened" BiCMOS. 3.5. A 1.8 GH.z 16-modulus /64-/79 Prescaler in 0.25 mum CMOS. 3.6. A 12 GHz /128 Prescaler in 0.25 mum CMOS. 3.7. Conclusion.

4: Monolithic CMOS LC-VCOs. 4.1. Introduction. 4.2. General Oscillator Theory. 4.3. A Design-Oriented Non-Linear Phase Noise Theory. 4.4. Integrated LC-tanks in CMOS. 4.5. The VCO Circuit Design. 4.6. Implementations. 4.7. Comparison with Published State-of-the-Art VCOs. 4.8. Conclusion.

5: Monolithic Phase Loops. 5.1. Introduction. 5.2. Loop Filter Topology Selection. 5.3. Dual-Path Fourth-Order PLL. 5.4. The PLL Building Block Circuits. 5.5. Experimental Results. 5.6. Conclusion.

6: A 1.8 GHz CMOS &Dgr;&Sgr; Fractional-N Frequency Synthesizer. 6.1. Introduction. 6.2. The Fractional-N Principle. 6.3. Conventional Fractional Compensation Methods. 6.4. &Dgr;&Sgr; Modulation in Fractional-N Synthesis. 6.5. &Dgr;&Sgr; Modulators for Fractional-N Synthesis. 6.6. The Theoretical &Dgr;&Sgr; Phase Noise Analysis. 6.7. A Fast Non-Linear &Dgr;&Sgr; Phase Noise Analysis Method. 6.8. The Fractional-N Synthesizer Circuit Design. 6.9. Experimental Results. 6.10. Conclusion.

7: Conclusions. 7.1. A 2V CMOS Cellular Transceiver Front-End. 7.2. Main Contributions and Achievements. 7.3. Epilogue.

A: &Dgr;&Sgr; Modulators with DC-inputs.

B: Additional Results of the Non-Linear Analysis for Fractional-N Synthesizers. Index. Bibliography.