VHDL for Logic Synthesis, 3/e (Hardcover)
暫譯: 邏輯合成的 VHDL,第 3 版 (精裝本)
Andrew Rushton
- 出版商: Wiley
- 出版日期: 2011-04-25
- 售價: $3,660
- 貴賓價: 9.5 折 $3,477
- 語言: 英文
- 頁數: 484
- 裝訂: Hardcover
- ISBN: 0470688475
- ISBN-13: 9780470688472
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相關翻譯:
用於邏輯綜合的 VHDL(第3版) (VHDL for Logic Synthesis, 3/e) (簡中版)
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商品描述
Making VHDL a simple and easy-to-use hardware description language
Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types.
This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features.
Features to this edition include:
- a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies
- a design style that results in long design lifetimes, maximum design reuse and easy technology retargeting
- a new chapter on a large scale design example based on a digital filter from design objective and design process, to testing strategy and test benches
- a chapter on writing test benches, with everything needed to implement a test-based design strategy
- extensive coverage of data path design, including integer, fixed-point and floating-point arithmetic, logic circuits, shifters, tristate buses, RAMs, ROMs, state machines, and decoders
Focused specifically on logic synthesis, this book is for professional hardware engineers using VHDL for logic synthesis, and digital systems designers new to VHDL but familiar with digital systems. It offers all the knowledge and tools needed to use VHDL for logic synthesis. Organised in themed chapters and with a comprehensive index, this complete reference will also benefit postgraduate students following courses on microelectronics or VLSI/ semiconductors and digital design.
商品描述(中文翻譯)
製作 VHDL 成為一種簡單易用的硬體描述語言
許多第一次接觸 VHDL(非常高速集成電路硬體描述語言)的工程師可能會感到不知所措。本書填補了 VHDL 語言與邏輯綜合所產生的硬體之間的鴻溝,清晰地組織內容,從組合邏輯、類型和運算子等基礎知識開始,經過三態匯流排、寄存器組和記憶體等特殊結構,直到開發自己的套件、撰寫測試平台以及使用各種綜合類型等進階主題。
本第三版已大幅重寫,以納入新的 VHDL-2008 特性,這些特性使得固定點和浮點硬體的綜合成為可能。全書經過廣泛更新,以反映現代邏輯綜合的使用情況,並包含完整的案例研究以展示更新的特性。
本版的特色包括:
- 一個通用的 VHDL 子集,能在多種不同的綜合系統中運作,針對非常廣泛的技術
- 一種設計風格,能夠實現長期的設計壽命、最大化的設計重用和簡易的技術重定向
- 一個關於大型設計範例的新章節,基於數位濾波器,涵蓋設計目標、設計過程、測試策略和測試平台
- 一個關於撰寫測試平台的章節,提供實施基於測試的設計策略所需的一切
- 廣泛涵蓋數據通路設計,包括整數、固定點和浮點運算、邏輯電路、移位器、三態匯流排、隨機存取記憶體(RAM)、唯讀記憶體(ROM)、狀態機和解碼器
本書專注於邏輯綜合,適合使用 VHDL 進行邏輯綜合的專業硬體工程師,以及對 VHDL 仍不熟悉但熟悉數位系統的數位系統設計師。它提供了使用 VHDL 進行邏輯綜合所需的所有知識和工具。內容以主題章節組織,並附有全面的索引,這本完整的參考書也將惠及修讀微電子或 VLSI/半導體及數位設計課程的研究生。