Digital Design and Modeling with VHDL and Synthesis
暫譯: 使用 VHDL 進行數位設計與建模及綜合

Name: Digital Design and Modeling with VHDL and Synthesis
Price: 4674 TWD
Availability: OnlineOnly
Author: Chang, K. C.
ISBN: 0818677163

Chang, K. C.

出版商: IEEE
出版日期: 1997-10-18
售價: $4,920
貴賓價: 9.5 折 $4,674
語言: 英文
頁數: 345
裝訂: Quality Paper - also called trade paper
ISBN: 0818677163
ISBN-13: 9780818677168

海外代購書籍(需單獨結帳)

商品描述

Digital Systems Design with VHDL and Synthesis presents an integrated approach to digital design principles, processes, and implementations to help the reader design much more complex systems within a shorter design cycle. This is accomplished by introducing digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together.

The author focuses on the ultimate product of the design cycle: the implementation of a digital design. VHDL coding, synthesis methodologies and verification techniques are presented as tools to support the final design implementation. Readers will understand how to apply and adapt techniques for VHDL coding, verification, and synthesis to various situations.

Digital Systems Design with VHDL and Synthesis is a result of K.C. Chang's practical experience in both design and as an instructor. Many of the design techniques and considerations illustrated throughout the chapters are examples of viable designs. His teaching experience leads to a step-by-step presentation that addresses common mistakes and hard-to-understand concepts in a way that eases learning.

Unique features of the book include the following:

VHDL code explained line by line to capture the logic behind the design concepts
VHDL is verified using VHDL test benches and simulation tools
Simulation waveforms are shown and explained to verify design correctness
VHDL code is synthesized and commands and strategies are discussed. Synthesized schematics and results are analyzed for area and timing
Variations on the design techniques and common mistakes are addressed; Demonstrated standard cell, gate array, and FPGA three design processes
Each with a complete design case study
Test bench, post-layout verification, and test vector generation processes.

Practical design concepts and examples are presented with VHDL code, simulation waveforms, and synthesized schematics so that readers can better understand their correspondence and relationships.

商品描述(中文翻譯)

《數位系統設計與 VHDL 及綜合》提供了一種整合的數位設計原則、流程和實現方法，幫助讀者在更短的設計週期內設計出更複雜的系統。這是通過將數位設計概念、VHDL 編碼、VHDL 模擬、綜合命令和策略一起介紹來實現的。

作者專注於設計週期的最終產品：數位設計的實現。VHDL 編碼、綜合方法論和驗證技術被呈現為支持最終設計實現的工具。讀者將了解如何將 VHDL 編碼、驗證和綜合的技術應用和調整到各種情況中。

《數位系統設計與 VHDL 及綜合》是 K.C. Chang 在設計和教學方面的實踐經驗的結果。書中各章節所示的許多設計技術和考量都是可行設計的範例。他的教學經驗使得內容以逐步的方式呈現，針對常見錯誤和難以理解的概念進行解釋，從而減輕學習的難度。

本書的獨特特點包括：
- VHDL 代碼逐行解釋，以捕捉設計概念背後的邏輯
- 使用 VHDL 測試平台和模擬工具對 VHDL 進行驗證
- 顯示和解釋模擬波形以驗證設計的正確性
- VHDL 代碼進行綜合，並討論命令和策略。分析綜合後的原理圖和結果的面積和時序
- 討論設計技術的變化和常見錯誤；展示標準單元、閘陣列和 FPGA 三種設計流程
- 每種設計都有完整的案例研究
- 測試平台、佈局後驗證和測試向量生成過程。

實用的設計概念和範例以 VHDL 代碼、模擬波形和綜合原理圖的形式呈現，幫助讀者更好地理解它們之間的對應和關係。

作者簡介

Kwang-chih Chang, commonly known as K.C. Chang, was a Chinese-American archaeologist and sinologist. He was the John E. Hudson Professor of archaeology at Harvard University, Vice-President of the Academia Sinica, and a curator at the Peabody Museum of Archaeology and Ethnology.