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商品描述
Verilog Hardware Description Language (HDL) is the state-of-the-art method for designing digital and computer systems. Ideally suited to describe both combinational and clocked sequential arithmetic circuits, Verilog facilitates a clear relationship between the language syntax and the physical hardware. It provides a very easy-to-learn and practical means to model a digital system at many levels of abstraction.
Computer Arithmetic and Verilog HDL Fundamentals details the steps needed to master computer arithmetic for fixed-point, decimal, and floating-point number representations for all primary operations. Silvaco International’s SILOS, the Verilog simulator used in these pages, is simple to understand, yet powerful enough for any application. It encourages users to quickly prototype and de-bug any logic function and enables single-stepping through the Verilog source code. It also presents drag-and-drop abilities.
Introducing the three main modeling methods—dataflow, behavioral, and structural—this self-contained tutorial—
- Covers the number systems of different radices, such as octal, decimal, hexadecimal, and binary-coded variations
- Reviews logic design fundamentals, including Boolean algebra and minimization techniques for switching functions
- Presents basic methods for fixed-point addition, subtraction, multiplication, and division, including the use of decimals in all four operations
- Addresses floating-point addition and subtraction with several numerical examples and flowcharts that graphically illustrate steps required for true addition and subtraction for floating-point operands
- Demonstrates floating-point division, including the generation of a zero-biased exponent
Designed for electrical and computer engineers and computer scientists, this book leaves nothing unfinished, carrying design examples through to completion. The goal is practical proficiency. To this end, each chapter includes problems of varying complexity to be designed by the reader.
商品描述(中文翻譯)
Verilog 硬體描述語言 (HDL) 是設計數位和計算機系統的最先進方法。它非常適合描述組合邏輯和時脈驅動的序列算術電路,Verilog 促進了語言語法與實體硬體之間的清晰關係。它提供了一種非常易於學習且實用的方式,以在多個抽象層次上建模數位系統。
**計算機算術與 Verilog HDL 基礎** 詳細說明了掌握固定點、十進位和浮點數表示的計算機算術所需的步驟,涵蓋所有主要操作。Silvaco International 的 SILOS 是本書中使用的 Verilog 模擬器,簡單易懂,但對於任何應用來說都足夠強大。它鼓勵用戶快速原型設計和除錯任何邏輯功能,並能逐步執行 Verilog 原始碼。它還提供了拖放功能。
本自包含的教程介紹了三種主要建模方法——數據流、行為和結構——
- 涵蓋不同基數的數字系統,例如八進位、十進位、十六進位和二進位編碼變體
- 回顧邏輯設計基礎,包括布林代數和開關函數的最小化技術
- 提供固定點加法、減法、乘法和除法的基本方法,包括在所有四個操作中使用十進位
- 討論浮點加法和減法,並提供幾個數值範例和流程圖,圖形化地說明浮點操作數進行真實加法和減法所需的步驟
- 演示浮點除法,包括生成零偏置指數
本書專為電機和計算機工程師及計算機科學家設計,沒有留下任何未完成的內容,將設計範例帶到完成。其目標是實用的熟練度。為此,每章都包括不同複雜度的問題,供讀者設計。