Verification Techniques for System-Level Design (Hardcover) (系統級設計的驗證技術)

Masahiro Fujita, Indradeep Ghosh, Mukul Prasad

Verification Techniques for System-Level Design (Hardcover)
  • 出版商: Morgan Kaufmann
  • 出版日期: 2007-11-01
  • 售價: $3,730
  • 貴賓價: 9.5 折 $3,544
  • 語言: 英文
  • 頁數: 256
  • 裝訂: Hardcover
  • ISBN: 0123706165
  • ISBN-13: 9780123706164

    • 海外代購書籍(需單獨結帳)

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Description

This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs.

First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs.
Formal verification of high-level designs (RTL or higher).
Verification techniques are discussed with associated system-level design methodology.

商品描述(中文翻譯)

本書將解釋如何使用形式和半形式驗證技術來驗證系統單晶片（SoC）邏輯設計。需要解決的關鍵問題是設計的功能是否符合設計者的意圖。模擬已被用於檢查SoC設計的正確性（如功能驗證），但許多微妙的設計錯誤無法通過模擬捕捉到。最近，形式驗證因其提供設計正確性的數學證明而受到更多關注。到目前為止，大多數有關形式驗證的書籍針對的是寄存器傳輸級（RTL）或更低級別的設計。為了提高設計生產力，及早調試設計至關重要。也就是說，設計應在非常抽象的設計層次（高於RTL）上完全驗證。本書涵蓋了系統級設計的高級形式和半形式驗證技術的各個方面。

本書是第一本涵蓋所有形式和半形式、高級（高於RTL）設計驗證方面的書籍，專注於SoC設計。高級設計（RTL或更高）的形式驗證。驗證技術將與相關的系統級設計方法論進行討論。

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