Low Power Direct Digital Frequency Synthesizer Using FPGA: Design,Simulation,and Implementation (Paperback)
Mohamed Elsayes
- 出版商: VDM Verlag
- 出版日期: 2010-06-08
- 售價: $2,440
- 貴賓價: 9.5 折 $2,318
- 語言: 英文
- 頁數: 136
- 裝訂: Paperback
- ISBN: 3639261976
- ISBN-13: 9783639261974
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相關分類:
FPGA
海外代購書籍(需單獨結帳)
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相關主題
商品描述
This Book introduces a new architecture design for Direct Digital Frequency Synthesizer, the design is developed using top-down design flow from behavioral modeling down to the implementation process. The proposed architecture is intended for use in spread spectrum such as, frequency hopping transceiver and any other digital transceiver and aims to reduce the frequency switching time of the synthesizer and reduce power consumption of synthesizer compared to conventional designs. In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The proposed architecture has been designed, simulated and synthesized using(XC4010xl) XILINX FPGA,with 3.3v supply voltage. The power consumption is 0.396 W at 100MHz clock frequency. The Spurious-Free Dynamic Range (SFDR) is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz. This book will include an introduction to the basic DDFS architecture and explain the modification added to the conventional DDFS to improve its performance. Also it explains the types of frequency synthesizer in modern transceivers.
商品描述(中文翻譯)
本書介紹了一種新的直接數位頻率合成器(Direct Digital Frequency Synthesizer)架構設計,該設計採用自上而下的設計流程,從行為建模到實現過程進行開發。所提出的架構旨在用於擴頻技術,例如頻率跳躍收發器及其他數位收發器,並旨在減少合成器的頻率切換時間,並相較於傳統設計降低合成器的功耗。為了避免高功耗,設計中不使用ROM,而是採用分段線性近似。所提出的架構已使用(XC4010xl) XILINX FPGA進行設計、模擬和合成,供電電壓為3.3V。在100MHz時鐘頻率下,功耗為0.396 W。其無雜訊動態範圍(Spurious-Free Dynamic Range, SFDR)在低合成頻率下優於59 dBc,頻率解析度為1.5 kHz。本書將包括對基本DDFS架構的介紹,並解釋對傳統DDFS所做的修改以改善其性能。此外,還將解釋現代收發器中頻率合成器的類型。