System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications, 3/e (Hardcover)
暫譯: System Verilog 斷言與功能覆蓋：語言、方法論與應用指南，第3版 (精裝本)

Mehta, Ashok B.

System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications, 3/e (Hardcover)

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商品描述

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. 

 

This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures.

·         Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;

·         Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies;

·         Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;

·         Explains each concept in a step-by-step fashion and applies it to a practical real life example;

 

·         Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.

商品描述(中文翻譯)

這本書提供了一個實作導向的指南，專注於 SystemVerilog Assertions 和 Functional Coverage 的語言及方法論。讀者將從逐步學習 SystemVerilog Assertions 和 Functional Coverage 的語言及方法論細微差異中受益，這將使他們能夠發現隱藏且難以找到的錯誤，直接指向錯誤的來源，提供一種乾淨且簡單的方式來建模複雜的時序檢查，並客觀地回答「我們是否已經功能驗證了所有內容」這個問題。這本書由一位專業的 ASIC/SoC/CPU 和 FPGA 設計及驗證的最終用戶撰寫，通過易於理解的範例、模擬日誌和來自真實專案的應用來解釋每個概念。讀者將能夠應對功能驗證的複雜檢查器建模和功能覆蓋的全面覆蓋模型，從而大幅減少設計、除錯和覆蓋的時間。

這本更新的第三版針對 IEEE-1800 (2012) LRM 中發布的最新功能集進行了修訂，包括許多額外的運算子和特性。此外，許多並行 Assertions/Operators 的解釋也得到了增強，增加了更多的範例和圖示。

・ 完整涵蓋最新的 IEEE-1800 2012 LRM 語法和語義；

・ 涵蓋 SystemVerilog Assertions 和 SystemVerilog Functional Coverage 語言及方法論；

・ 提供基於 Assertions 的驗證和功能覆蓋方法論的實際應用，包括其何、如何及為何；

・ 以逐步的方式解釋每個概念，並將其應用於實際的真實範例；

・ 包含 6 個實用的 LAB，讓讀者能夠將書中解釋的概念付諸實踐。

作者簡介

 

Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium design team) and after a route of a couple of startups, worked at Applied Micro and TSMC. He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs and at TSMC he released two industry standard Reference Flows that establish Reuse of Verification Environment from ESL to RTL. Lately, he has been researching 3DIC design verification challenges at TSMC which is where SystemVerilog Assertions played an instrumental role in stacked die SoC design verification.

Ashok earned an MSEE from University of Missouri. He holds 18 U.S. Patents in the field of SoC and 3DIC design verification.

 

 

 

 

作者簡介(中文翻譯)

Ashok Mehta 在 ASIC/SoC 設計與驗證領域工作超過 20 年。他的職業生涯始於數位設備公司（Digital Equipment Corporation, DEC），擔任 CPU 設計工程師。之後，他在 Data General、Intel（第一個 Pentium 設計團隊）工作，經過幾家初創公司的歷練後，加入了 Applied Micro 和 TSMC。他是 Verilog 的早期採用者之一，並參與了 Verilog、VHDL、iHDL（Intel HDL）和 SDF（標準延遲格式）技術小組委員會。他也一直是 ESL（電子系統級）設計的支持者，在 TSMC，他發布了兩個行業標準的參考流程，建立了從 ESL 到 RTL 的驗證環境重用。最近，他在 TSMC 研究 3DIC 設計驗證的挑戰，這裡 SystemVerilog Assertions 在堆疊晶片 SoC 設計驗證中發揮了重要作用。

Ashok 獲得了密蘇里大學的電機工程碩士學位。他在 SoC 和 3DIC 設計驗證領域擁有 18 項美國專利。

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