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商品描述
Description
Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.
商品描述(中文翻譯)
**描述**
《低電壓 CMOS 對數壓縮類比設計》詳細介紹了在 CMOS 技術中針對非常低電壓和低功耗的系統單晶片設計的最先進類比電路技術。所提出的策略主要基於兩個基礎:瞬時對數壓縮理論(Instantaneous Log Companding Theory)和在亞閾值區域運作的 MOSFET。前者允許在非常低電壓操作下內部壓縮電壓動態範圍,而後者則與 CMOS 技術相容,適用於低功耗電路。關於對數壓縮的 MOS 晶體管特定建模所需的背景知識在開頭提供。根據這一通用方法,提出並分析了一整套 CMOS 基本構建塊,適用於各種類比信號處理。特別是,涵蓋的領域包括:放大和自動增益控制(AGC)、任意濾波、PTAT 生成和脈衝持續時間調變(PDM)。對於每個主題,考慮了幾個案例研究以說明設計方法論。此外,報告了在 1.2um 和 0.35um CMOS 技術中的集成範例,以驗證設計方程式與實驗數據之間的良好一致性。所得到的類比電路拓撲展現出非常低電壓(即 1V)和低功耗(幾十微安)的能力。除了這些特定的設計範例外,還展示了一個在助聽器領域的實際工業應用,作為所有提出的基本構建塊的主要示範。這個系統單晶片展現出真正的 1V 操作、高靈活性(透過數位可編程性)和非常低的功耗(約 300uA,包括 Class-D 放大器)。因此,報告的 ASIC 可以滿足一整套常見助聽器模型的規格。總之,本書適合於工業 ASIC 設計師,他們可以將其內容應用於標準 CMOS 技術中非常低功耗系統單晶片的合成,以及電子工程現代電路設計的教師。