Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design (Hardocver) (縮短ASIC與定制之間的差距：高效能ASIC設計的工具與技術)

David Chinnery, Kurt Keutzer

Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design (Hardocver)
  • 出版商: Springer
  • 出版日期: 2002-06-30
  • 售價: $6,980
  • 貴賓價: 9.5 折 $6,631
  • 語言: 英文
  • 頁數: 414
  • 裝訂: Hardcover
  • ISBN: 1402071132
  • ISBN-13: 9781402071133

    • 立即出貨 (庫存=1)

相關主題

商品描述

Description

This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times.

Important topics include:

  • Improving performance through microarchitecture;
  • Timing-driven floorplanning;
  • Controlling and exploiting clock skew;
  • High performance latch-based design in an ASIC methodology;
  • Automatically identifying and synthesizing complex logic gates;
  • Automated cell sizing to increase performance and reduce power;
  • Controlling process variation.

These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation. 

 

Table of Contents

Preface. List of trademarks. 1. Introduction and Overview of the Book; D. Chinnery, K. Keutzer.
Contributing Factors.
2. Improving Performance through Microarchitecture; D. Chinnery, K. Keutzer. 3. Reducing the Timing Overhead; D. Chinnery, K. Keutzer. 4. High-Speed Logic, Circuits, Libraries and Layout; A. Chang, et al. 5. Finding Peak Performance in a Process; D. Chinnery, K. Keutzer.
Design Techniques.
6. Physical Prototyping Plans for High Performance; M. Courtoy, et al. 7. Automatic Replacement of Flip-Flops by Latches in ASIC's; D. Chinnery, et al. 8. Useful-Skew Clock Synthesis Boosts ASIC Performance; W. Dai, D. Staepelaere. 9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing; M. Côté, P. Hurat. 10. Design Optimization with Automated Flex-Cell Creation; D. Bhattacharya, V. Boppana. 11. Exploiting Structure and Managing Wires to Increase Density and Performance; A. Chang, W.J. Dally. 12. Semi-Custom Methods in a High-Performance Microprocessor Design; G.A. Northrop. 13. Controlling Uncertainty in High Frequency Designs; S.E. Rich, et al. 14. Increasing Circuit Performance through Statistical Design Techniques; M. Orshansky.
Design Examples.
15. Achieving 550MHz in a Standard Cell ASIC Methodology; D. Chinnery, et al. 16. The iCORE® 520MHz Synthesizable CPU Core; N. Richardson, et al. 17. Creating Synthesizable ARM Processors with Near Custom Performance; D. Flynn, M. Keating.

商品描述(中文翻譯)

描述

本書詳細介紹了高性能ASIC設計的設計工具和技術。使用這些技術，ASIC設計的性能可以提高兩到三倍。

重要的主題包括：
- 通過微架構改進性能；
- 基於時序的布局；
- 控制和利用時鐘偏移；
- ASIC方法中的高性能鎖存器設計；
- 自動識別和合成複雜邏輯門；
- 自動單元大小調整以提高性能和降低功耗；
- 控制製程變異性。

這些技術通過運行在相同製程世代中兩到三倍速度的設計來加以說明。

目錄

前言。商標列表。1. 本書介紹和概述；D. Chinnery, K. Keutzer.
貢獻因素。
2. 通過微架構改進性能；D. Chinnery, K. Keutzer.
3. 減少時序開銷；D. Chinnery, K. Keutzer.
4. 高速邏輯、電路、庫和佈局；A. Chang, et al.
5. 在製程中找到最高性能；D. Chinnery, K. Keutzer.
設計技術。
6. 高性能的物理原型計劃；M. Courtoy, et al.
7. 在ASIC中自動替換觸發器為鎖存器；D. Chinnery, et al.
8. 有用的偏差時鐘合成提升ASIC性能；W. Dai, D. Staepelaere.
9. 通過晶體管級單元大小調整實現更快更低功耗的基於單元的設計；M. Côté, P. Hurat.
10. 通過自動靈活單元創建進行設計優化；D. Bhattacharya, V. Boppana.
11. 利用結構和管理線路以增加密度和性能；A. Chang, W.J. Dally.
12. 高性能微處理器設計中的半定制方法；G.A. Northrop.
13. 控制高頻設計中的不確定性；S.E. Rich, et al.
14. 通過統計設計技術提高電路性能；M. Orshansky.
設計示例。
15. 在標準單元ASIC方法中實現550MHz；D. Chinnery, et al.
16. iCORE® 520MHz可合成CPU核心；N. Richardson, et al.
17. 創建具有接近定制性能的可合成ARM處理器；D. Flynn, M. Keating.

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