Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms (Hardcover
暫譯: 網路晶片整合系統級建模的多處理器平台

Tim Kogel, Rainer Leupers, Heinrich Meyr

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms (Hardcover
  • 出版商: Springer
  • 出版日期: 2006-07-05
  • 售價: $6,800
  • 貴賓價: 9.5 折 $6,460
  • 語言: 英文
  • 頁數: 186
  • 裝訂: Hardcover
  • ISBN: 1402048254
  • ISBN-13: 9781402048258

    • 海外代購書籍(需單獨結帳)

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Description

The drastic performance, flexibility and energy-efficiency requirements of embedded applications drive the System-on-Chip integration towards heterogeneous multiprocessor platforms. Electronic System Level (ESL) design methodologies and tools have emerged to tackle the challenges of such complex SoC designs prior to RTL and silicon availability. In particular SystemC based Transaction Level Modeling (TLM) has matured as a standards-based approach to model SoC platforms for the purpose of Software development, system integration and verification.

In response to the vast complexity of heterogeneous multi-processor platforms the "Architects View" is emerging as a new TLM use-case to address the architecture definition and application mapping by means of timing approximate transaction-level models.

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.

 

Table of contents

Foreword. Preface.

1. INTRODUCTION. 1.1 Organization of the Book Chapters.

2. EMBEDDED SOC APPLICATIONS. 2.1 Networking Domain. 2.2 Multimedia Domain. 2.3 Wireless Communications. 2.4 Application Trends. 2.5 First Order Application Partitioning.

3. CLASSIFICATION OF PLATFORM ELEMENTS. 3.1 Architecture Metrics. 3.2 Processing Elements. 3.3 On-Chip Communication. 3.4 Summary.

4. SYSTEM LEVEL DESIGN PRINCIPLES. 4.1 The Platform Based Design Paradigm. 4.2 Design Phases. 4.3 Abstraction Mechanisms. 4.4 Models of Computation. 4.5 Object versus Actor Oriented Design. 4.6 System Level Design Requirements.

5. RELATED WORK. 5.1 Traditional HW/SW Co-Design. 5.2 SystemC based Transaction Level Modeling. 5.3 Current Research on MP-SoC Design Methodologies. 5.4 Summary.

6. METHODOLOGY OVERVIEW. 6.1 Application Modeling. 6.2 Architecture Modeling. 6.3 Envisioned Design Flow. 6.4 MP-SoC Simulation Framework.

7. UNIFIED TIMING MODEL. 7.1 Tagged Signal Model Introduction. 7.2 Reactive Process Network. 7.3 Architecture Model. 7.4 Performance Metrics. 7.5 Summary.

8. MP-SOC SIMULATION FRAMEWORK. 8.1 The Generic Synchronization Protocol. 8.2 Generic VPU Model. 8.3 NoC Framework. 8.4 Tool Support. 8.5 Summary.

9. CASE STUDY. 9.1 IPv4 Forwarding with QoS Support. 9.2 Intel IXP2400 Reference NPU. 9.3 Custom IPv4 Platform. 9.4 Simulation Results.

10. SUMMARY.

Appendices. A The OSCI TLM Standard. B The OCPIP TL3 Channel. C The Architects View Framework.

List of Figures. List of Tables. References. Index.

商品描述(中文翻譯)

**描述**

嵌入式應用對性能、靈活性和能效的嚴格要求推動了系統單晶片（System-on-Chip, SoC）整合朝向異構多處理器平台發展。電子系統級（Electronic System Level, ESL）設計方法論和工具已經出現，以應對在 RTL 和矽片可用性之前，這類複雜 SoC 設計所面臨的挑戰。特別是基於 SystemC 的交易級建模（Transaction Level Modeling, TLM）已經成熟，成為一種基於標準的方法，用於建模 SoC 平台，以便進行軟體開發、系統整合和驗證。

為了應對異構多處理器平台的巨大複雜性，"架構師視角"（Architects View）作為一種新的 TLM 使用案例正在出現，旨在通過時間近似的交易級模型來解決架構定義和應用映射的問題。

**集成系統級建模的網路晶片（Network-on-Chip）啟用的多處理器平台**首先對 SoC 平台和 ESL 設計方法論領域的最新發展進行了全面更新。主要貢獻是對時間近似抽象層級建模框架的嚴格定義。隨後，本書介紹了一組工具，用於創建和探索時間近似的 SoC 平台模型。

**目錄**

前言。序言。

1. 引言。1.1 本書章節組織。

2. 嵌入式 SoC 應用。2.1 網路領域。2.2 多媒體領域。2.3 無線通訊。2.4 應用趨勢。2.5 一階應用分區。

3. 平台元素的分類。3.1 架構指標。3.2 處理元素。3.3 晶片內通訊。3.4 總結。

4. 系統級設計原則。4.1 基於平台的設計範式。4.2 設計階段。4.3 抽象機制。4.4 計算模型。4.5 物件導向與演員導向設計。4.6 系統級設計要求。

5. 相關工作。5.1 傳統硬體/軟體共同設計。5.2 基於 SystemC 的交易級建模。5.3 當前 MP-SoC 設計方法論的研究。5.4 總結。

6. 方法論概述。6.1 應用建模。6.2 架構建模。6.3 設計流程展望。6.4 MP-SoC 模擬框架。

7. 統一時間模型。7.1 標記信號模型介紹。7.2 反應式過程網路。7.3 架構模型。7.4 性能指標。7.5 總結。

8. MP-SoC 模擬框架。8.1 通用同步協議。8.2 通用 VPU 模型。8.3 NoC 框架。8.4 工具支援。8.5 總結。

9. 案例研究。9.1 支援 QoS 的 IPv4 轉發。9.2 Intel IXP2400 參考 NPU。9.3 自訂 IPv4 平台。9.4 模擬結果。

10. 總結。

附錄。A OSCI TLM 標準。B OCPIP TL3 通道。C 架構師視角框架。

圖表清單。表格清單。參考文獻。索引。

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