Advances in Embedded and Fan-Out Wafer Level Packaging Technologies
暫譯: 嵌入式與扇出式晶圓級封裝技術的進展

Beth Keser (Editor), Steffen Kroehnert (Editor)

  • 出版商: Wiley
  • 出版日期: 2019-02-12
  • 定價: $4,400
  • 售價: 9.5$4,180
  • 語言: 英文
  • 頁數: 528
  • 裝訂: Hardcover
  • ISBN: 1119314135
  • ISBN-13: 9781119314134
  • 相關分類: 嵌入式系統
  • 立即出貨 (庫存 < 3)

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商品描述

Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges

 

Embedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it  is processed, what is driving its development, and the pros and cons.

 

Filled with contributions from some of the field’s leading experts, Advances in Embedded and Fan-Out Wafer Level Packaging Technologies begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions.

 

  • Discusses specific company standards and their development results
  • Content relates to practice as well as to contemporary and future challenges in electronics system integration and packaging

 

Advances in Embedded and Fan-Out Wafer Level Packaging Technologies will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.

商品描述(中文翻譯)

探討嵌入式和扇出晶圓級封裝(FO-WLP)技術的優勢、潛在應用領域、業界可用的封裝結構、流程以及材料挑戰

嵌入式和扇出晶圓級封裝(FO-WLP)技術在過去15年中已在業界發展,並在近十年內進入高產量製造。本書涵蓋了這項新封裝技術所取得的進展,並討論了它為電子封裝產業和供應鏈帶來的諸多好處。它提供了該領域主要技術類型的簡明概述,包括可用的技術、處理方式、推動其發展的因素以及優缺點。

本書由該領域的一些領先專家撰寫,嵌入式和扇出晶圓級封裝技術的進展首先回顧了該技術的歷史。接著,探討了最大的技術和市場趨勢。其他部分專注於晶片優先的FO-WLP、晶片後置的FO-WLP、嵌入式晶片封裝、材料挑戰、設備挑戰以及由此產生的技術融合。


  • 討論特定公司的標準及其發展成果

  • 內容與實踐相關,並涉及當前及未來電子系統整合和封裝的挑戰

嵌入式和扇出晶圓級封裝技術的進展將吸引在OEM、IDM、IFM、OSAT、矽晶圓廠、材料供應商、設備供應商和CAD工具供應商工作的微電子封裝工程師、經理和決策者。對於從事微電子封裝研究的教授和研究生來說,這也是一本極好的書籍。