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商品描述
Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry.
商品描述(中文翻譯)
模型階數簡化（Model Order Reduction, MOR）技術降低了 VLSI 設計的複雜性，為更高的運行速度和更小的特徵尺寸鋪平了道路。本書系統性地介紹了在一般線性電路中使用的關鍵 MOR 方法，並通過實際案例來說明每種算法的優缺點。在回顧傳統的基於投影的技術後，內容進一步涵蓋了 VLSI 設計的更先進的 MOR 方法，包括 HMOR、被動截斷平衡實現（Passive Truncated Balanced Realization, TBR）方法、通過 VPEC 模型進行的高效電感建模，以及結構保持的 MOR 技術。在可能的情況下，數值方法從 CAD 工程師的角度進行探討，避免複雜的數學，讓讀者能夠面對實際設計問題並開發更有效的工具。本書包含實用範例和超過 100 幅插圖，適合電機與計算機工程的研究人員和研究生，以及在 VLSI 設計行業工作的實務者。
