Static Timing Analysis for Nanometer Designs: A Practical Approach (Hardcover)
暫譯: 奈米設計的靜態時序分析:實用方法 (精裝版)

J. Bhasker, Rakesh Chadha

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商品描述

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts.

The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology.

This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.

商品描述(中文翻譯)

本書涵蓋了如單元時序與功耗建模、互連建模與分析、延遲計算、串擾、噪聲以及使用靜態時序分析進行晶片時序驗證等主題。對於這些主題,本書提供了理論背景以及詳細的範例來闡述這些概念。

靜態時序分析的主題從驗證對於初學者有用的簡單模塊開始,然後擴展到複雜的奈米設計,深入探討如晶片內變異建模、時鐘閘控、半週期路徑以及源同步介面(如DDR)的時序等概念。串擾對時序和噪聲的影響也有涵蓋,並且介紹了階層設計方法的使用。

本書討論了CMOS邏輯閘、單元庫、時序弧、波形上升時間、單元電容、時序建模、互連寄生電容與耦合、佈局前後的互連建模、延遲計算、內部路徑及IO介面的時序約束規範分析。還涵蓋了如受控電流源時序和奈米技術的噪聲模型、高級建模與分析概念、功耗建模(包括主動功耗和漏電功耗)、串擾時序和串擾毛刺計算、半週期和多週期路徑的驗證、虛假路徑、同步介面等內容。