High Performance Integrated Circuit Design (Hardcover)
暫譯: 高效能集成電路設計 (精裝版)
Emre Salman, Eby G. Friedman
- 出版商: McGraw-Hill Education
- 出版日期: 2012-09-18
- 售價: $5,860
- 貴賓價: 9.5 折 $5,567
- 語言: 英文
- 頁數: 736
- 裝訂: Hardcover
- ISBN: 0071635769
- ISBN-13: 9780071635769
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相關主題
商品描述
The latest techniques for designing robust, high performance integrated circuits in nanoscale technologies Focusing on a new technological paradigm, this practical guide describes the interconnect-centric design methodologies that are now the major focus of nanoscale integrated circuits (ICs). High Performance Integrated Circuit Design begins by discussing the dominant role of on-chip interconnects and provides an overview of technology scaling. The book goes on to cover data signaling, power management, synchronization, and substrate-aware design.
Specific design constraints and methodologies unique to each type of interconnect are addressed. This comprehensive volume also explains the design of specialized circuits such as tapered buffers and repeaters for data signaling, voltage regulators for power management, and phase-locked loops for synchronization. This is an invaluable resource for students, researchers, and engineers working in the area of high performance ICs.
High Performance Integrated Circuit Design
Coverage includes:
Specific design constraints and methodologies unique to each type of interconnect are addressed. This comprehensive volume also explains the design of specialized circuits such as tapered buffers and repeaters for data signaling, voltage regulators for power management, and phase-locked loops for synchronization. This is an invaluable resource for students, researchers, and engineers working in the area of high performance ICs.
High Performance Integrated Circuit Design
Coverage includes:
- Technology scaling
- Interconnect modeling and extraction
- Signal propagation and delay analysis
- Interconnect coupling noise
- Power generation
- Power distribution networks
- CAD of power networks
- Techniques to reduce power supply noise
- Power dissipation
- Synchronization theory and tradeoffs
- Synchronous system characteristics
- On-chip clock generation
- Clock distribution networks
- Substrate noise in mixed-signal ICs
- Techniques to reduce substrate noise
商品描述(中文翻譯)
最新的技術用於設計穩健、高效能的納米級集成電路 本書專注於一種新的技術範式,描述了目前納米級集成電路(ICs)主要關注的以互連為中心的設計方法。本書《高效能集成電路設計》首先討論了片上互連的主導角色,並提供技術縮放的概述。接著,書中涵蓋了數據信號傳遞、電源管理、同步以及基板感知設計。
針對每種類型的互連,書中探討了特定的設計限制和獨特的方法論。這本全面的著作還解釋了專用電路的設計,例如用於數據信號傳遞的錐形緩衝器和重複器、用於電源管理的電壓調節器,以及用於同步的相位鎖定迴路。這是一本對於從事高效能集成電路領域的學生、研究人員和工程師來說,極具價值的資源。
《高效能集成電路設計》涵蓋的內容包括:
- 技術縮放
- 互連建模與提取
- 信號傳播與延遲分析
- 互連耦合噪聲
- 電源生成
- 電源分配網絡
- 電源網絡的CAD
- 減少電源噪聲的技術
- 功率耗散
- 同步理論與權衡
- 同步系統特性
- 片上時鐘生成
- 時鐘分配網絡
- 混合信號IC中的基板噪聲
- 減少基板噪聲的技術