Designing Network On-Chip Architectures in the Nanoscale Era
暫譯: 在奈米尺度時代設計片上網路架構

Flich, Jose, Bertozzi, Davide

Designing Network On-Chip Architectures in the Nanoscale Era

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商品描述

Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.

 

 

 

 

 

 

 

Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent products. They describe Tilera's TILE family of multicore processors, novel Intel products and research prototypes, and the TRIPS operand network (OPN). The last part reveals state-of-the-art solutions to hardware-related issues and explains how to efficiently implement the programming model at the network interface. In the appendix, the microarchitectural details of two switch architectures targeting multiprocessor system-on-chips (MPSoCs) and chip multiprocessors (CMPs) can be used as an experimental platform for running tests.

 

 

 

 

 

 

 

 

 

A stepping stone to the evolution of future chip architectures, this volume provides a how-to guide for designers of current NoCs as well as designers involved with 2015 computing platforms. It cohesively brings together fundamental design issues, alternative design paradigms and techniques, and the main design tradeoffs--consistently focusing on topics most pertinent to real-world NoC designers.

 

 

商品描述(中文翻譯)

超越孤立的研究理念和設計經驗，在奈米尺度時代設計片上網路架構涵蓋了片上網路（NoC）技術的基礎和設計方法。貢獻者根據自身的經驗教訓，提供了針對各種設計問題的強有力實用指導。

本書的第一部分探討網路的設計過程，重點關注交換器架構和設計的基本方面、拓撲選擇以及路由實現。在第二部分，貢獻者分享他們在業界的經驗，提供近期產品的路線圖。他們描述了Tilera的TILE系列多核心處理器、新穎的Intel產品和研究原型，以及TRIPS操作數網路（OPN）。最後一部分揭示了針對硬體相關問題的最先進解決方案，並解釋如何在網路介面上有效實現程式設計模型。在附錄中，針對多處理器系統單晶片（MPSoCs）和晶片多處理器（CMPs）的兩種交換器架構的微架構細節可作為運行測試的實驗平台。

作為未來晶片架構演變的踏腳石，本書為當前NoC設計師以及參與2015年計算平台的設計師提供了實用指南。它將基本設計問題、替代設計範式和技術，以及主要設計權衡有機地結合在一起，始終專注於與現實世界NoC設計師最相關的主題。

作者簡介

José Flich is an associate professor of computer architecture and technology at the Technical University of Valencia. Dr. Flich is the coordinator of the EU-funded NaNoC project; co-chair of the CAC, CASS, and INA-OCMC workshops; and co-developer of RECN, the only truly scalable congestion management technique proposed to date. He is also associate editor of the IEEE Transactions on Parallel and Distributed Systems. His research interests include high-performance interconnection networks for multiprocessor systems, clusters of workstations, and networks on-chip.

 

 

Davide Bertozzi is an assistant professor and leader of the Multi-Processor Systems-On-Chip research group at the University of Ferrara. Dr. Bertozzi is the general chair of the INA-OCMC workshop and an editorial board member of IET Computers & Digital Techniques. His research interests encompass multi-core digital integrated systems, with an emphasis on all aspects of system interconnect design.

 

 

作者簡介(中文翻譯)

José Flich 是瓦倫西亞理工大學的計算機架構與技術副教授。Flich 博士是歐盟資助的 NaNoC 項目的協調員；CAC、CASS 和 INA-OCMC 研討會的共同主席；以及 RECN 的共同開發者，這是迄今為止唯一真正可擴展的擁塞管理技術。他也是 IEEE Transactions on Parallel and Distributed Systems 的副編輯。他的研究興趣包括多處理器系統、高效能互連網路、工作站叢集和片上網路。

Davide Bertozzi 是費拉拉大學的助理教授及多處理器系統晶片研究小組的負責人。Bertozzi 博士是 INA-OCMC 研討會的總主席，以及 IET Computers & Digital Techniques 的編輯委員會成員。他的研究興趣涵蓋多核心數位整合系統，特別強調系統互連設計的各個方面。

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