Energy Efficient High Performance Processors: Recent Approaches for Designing Green High Performance Computing
暫譯: 能源效率高效能處理器：設計綠色高效能計算的最新方法

本書探討高效能計算（HPC）系統的能源效率技術，使用電源管理方法。採用逐步的方法，描述了現代處理器（如 Intel Sandy Bridge、Haswell、Skylake 及其他架構，例如 ARM）中所使用的電源管理流程、演算法和機制。此外，本書包含實際範例和最近的研究，展示現代處理器如何動態管理廣泛的功率範圍，從最低閒置功率狀態的幾毫瓦到渦輪狀態下的數十瓦。此外，本書解釋了在這個巨大功率範圍內如何管理熱量和電力供應。本書還討論了能源效率的不同指標，提出了幾種功率和能源估算的方法和應用，並展示了如何通過使用創新的功率估算方法和新演算法，使現代處理器能夠優化功率、能源和性能等指標。書中介紹了不同的功率估算工具，包括能夠在子處理器核心/執行緒粒度下細分現代處理器功耗的工具。本書還研究了減少功耗的軟體、韌體和硬體協調方法，例如一種編譯器輔助的電源管理方法，以克服功率波動。最後，本書檢視了動態快取調整和動態電壓與頻率調整（DVFS）在記憶體子系統中的韌體演算法。

Jawad Haj-Yahya received his BSc degree in Computer Science from Technion - Israel Institute of Technology, and his MSc and PhD degrees in Computer Science from the University of Haifa. Jawad worked as a power management architect for high-performance processors (Sandy Bridge, Haswell, Skylake, etc) in the Processors' Architecture group at the Intel Corporation for 13 years. Jawad's honors include the Intel Achievement Award (IAA), which is the highest award at Intel. His research interests include energy aware computing, power estimation and applications, and low power IC design. Recently Jawad has joined Nanyang Technology University at Singapore as a cyber security research scientist.
Prof. Avi Mendelson has a blend of industrial and academic experience in several different areas, such as computer architecture, operating systems, power management, reliability, high-performance computing and hardware security. He received his PhD from the ECE Department, University of Massachusetts at Amherst (UMASS) in 1990 and his BSc and MSc degrees from the Computer Science Department, Technion. He was the manager of the academic outreach program at Microsoft R&D Israel, where he initiated various innovation-based activities for students. Before that, he worked for 11 years as a senior researcher and principal engineer at Intel. Among his achievements at Intel, he was the chief architect of the CMP (multicore-on-chip) feature of the first dual-core processors Intel developed, for which he received the Intel Achievement Award (the highest award at Intel). Mendelson has published more than 130 papers in refereed journals, and at conferences and workshops. He completed a full term as an associate editor of IEEE Computer Architecture Letters (CAL) and now serves as an associate editor of IEEE Transactions on Computers.He served as program chair of a number of major conferences and as the general chair of the ISCA (International Symposium on Computer Architecture) in 2013. Recently he was elected to the Board of Governors of the IEEE Computer Society.
Prof. Yosi Ben-Asher received his PhD degree in Computer Science from the Hebrew University of Jerusalem. He is a professor at Computer Science Department, University of Haifa. He is currently leading several research projects including: P2NC a system to study probabilistic evaluation of Boolean circuits, a high-level synthesis compiler from C to Verilog with optimized memory layout, a silicon compiler that minimizes wire lengths, 1 K multicore chip and an ASIP compiler/CPU based on graph tiling. His research areas include compilers, EDA, parallel programming, ad-hoc networks and reconfigurable networks.
Prof. Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc from ALaRI, Switzerland and PhD from RWTH Aachen, Germany in 2002 and 2008 respectively. From 2008 to 2009, he worked as a member of consulting staff at CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group at RWTH Aachen, as a junior professor. Since September 2014, he has been an Assistant Professor at SCE, NTU.During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was later commercialized by a leading EDA vendor. He developed several high-level optimizations and verification flows for embedded processors. In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. Together with his doctoral students, Anupam proposed domain-specific, high-level synthesis for cryptography, high-level reliability estimation flows for embedded processors, generalisation of classic linear algebra kernels and a novel multi-layered coarse-grained reconfigurable architecture. In these areas, he has published as a (co)-author over 100 conference/ journal papers, several book chapters and a book. Anupam has served on various TPCs of top conferences, regularly reviews journal/conference articles and presented multiple invited seminars/tutorials at prestigious venues. He is a member of ACM and a senior member of IEEE.Anupam received Borcher's plaque from RWTH Aachen for his outstanding doctoral dissertation in 2008 and nomination for best IP award in DATE 2016.

Jawad Haj-Yahya 於以色列理工學院 (Technion) 獲得計算機科學學士學位，並於海法大學 (University of Haifa) 獲得計算機科學碩士及博士學位。Jawad 在英特爾公司 (Intel Corporation) 的處理器架構組擔任高效能處理器 (如 Sandy Bridge、Haswell、Skylake 等) 的電源管理架構師，工作了 13 年。Jawad 獲得的榮譽包括英特爾成就獎 (Intel Achievement Award, IAA)，這是英特爾的最高獎項。他的研究興趣包括能源感知計算、功率估算及應用，以及低功耗集成電路設計。最近，Jawad 加入新加坡南洋理工大學 (Nanyang Technology University) 擔任網路安全研究科學家。
Prof. Avi Mendelson 在計算機架構、作業系統、電源管理、可靠性、高效能計算和硬體安全等多個領域擁有工業和學術經驗。他於 1990 年在麻省大學阿默斯特分校 (University of Massachusetts at Amherst, UMASS) 的電子與計算機工程系獲得博士學位，並在以色列理工學院獲得學士和碩士學位。他曾擔任微軟以色列研發部的學術外展計畫經理，啟動了多項以創新為基礎的學生活動。在此之前，他在英特爾工作了 11 年，擔任高級研究員和首席工程師。在英特爾的成就中，他是英特爾開發的第一款雙核處理器的 CMP (多核晶片) 功能的首席架構師，並因此獲得英特爾成就獎 (英特爾的最高獎項)。Mendelson 在經過審核的期刊、會議和研討會上發表了超過 130 篇論文。他完成了 IEEE 計算機架構快報 (IEEE Computer Architecture Letters, CAL) 的副編輯全任期，現在擔任 IEEE 計算機學報 (IEEE Transactions on Computers) 的副編輯。他曾擔任多個主要會議的程式主席，並於 2013 年擔任 ISCA (國際計算機架構研討會) 的總主席。最近，他當選為 IEEE 計算機學會的理事會成員。
Prof. Yosi Ben-Asher 於耶路撒冷希伯來大學獲得計算機科學博士學位。他是海法大學計算機科學系的教授。目前，他正在領導幾個研究專案，包括：P2NC，一個研究布林電路的概率評估系統；從 C 到 Verilog 的高階合成編譯器，具有優化的記憶體佈局；一個最小化導線長度的矽編譯器；1 K 多核晶片；以及基於圖形平鋪的 ASIP 編譯器/CPU。他的研究領域包括編譯器、電子設計自動化 (EDA)、平行程式設計、臨時網路和可重構網路。
Prof. Anupam Chattopadhyay 於 2000 年在印度賈達夫普大學 (Jadavpur University) 獲得工程學士學位。2002 年，他在瑞士 ALaRI 獲得碩士學位，並於 2008 年在德國亞琛工業大學 (RWTH Aachen) 獲得博士學位。2008 年至 2009 年，他在印度諾伊達的 CoWare 研發部擔任顧問團隊成員。2010 年至 2014 年，他作為助理教授領導 RWTH Aachen 的 MPSoC 架構研究小組。自 2014 年 9 月以來，他一直擔任國立台灣大學 (NTU) SCE 的助理教授。在攻讀博士學位期間，他研究了從架構描述語言 LISA 自動生成 RTL 的技術，該技術後來被一家領先的 EDA 廠商商業化。他為嵌入式處理器開發了幾個高階優化和驗證流程。在他的博士論文中，他提出了一個基於語言的建模、探索和實現框架，用於部分可重構處理器。與他的博士生一起，Anupam 提出了針對密碼學的領域特定高階合成、嵌入式處理器的高階可靠性估算流程、經典線性代數核心的泛化以及一種新穎的多層粗粒度可重構架構。在這些領域，他作為 (共同) 作者發表了超過 100 篇會議/期刊論文、幾個書章和一本書。Anupam 曾在多個頂級會議的技術程序委員會 (TPC) 擔任成員，定期審查期刊/會議文章，並在多個知名場所進行多次受邀研討會/教程。他是 ACM 的成員，也是 IEEE 的資深會員。Anupam 於 2008 年因其傑出的博士論文獲得 RWTH Aachen 的 Borcher 獎牌，並於 2016 年被提名為 DATE 最佳 IP 獎。