Digital Design : Principles and Practices, 4/e (IE-Paperback)
暫譯: 數位設計:原則與實務,第4版 (IE-平裝本)
John F. Wakerly
- 出版商: Prentice Hall
- 出版日期: 2005-07-26
- 售價: $1,323
- 語言: 英文
- 頁數: 928
- ISBN: 981067791X
- ISBN-13: 9789810677916
-
相關分類:
數位影像處理 Digital-image、電子學 Eletronics、電路學 Electric-circuits
-
其他版本:
Digital Design: Principles and Practices (美國原版)
買這商品的人也買了...
-
$350$277 -
$880$695 -
$880$695 -
$650$514 -
$650$507 -
$550$435 -
$270$213 -
$690$587 -
$980$774 -
$690$538 -
$600$474 -
$1,560$1,326 -
$550$435 -
$620$484 -
$580$452 -
$1,200$948 -
$600$480 -
$880$695 -
$750$593 -
$780$616 -
$780$616 -
$360$284 -
$580$458 -
$260$234 -
$260$234
商品描述
Description
Appropriate for a first or second course in digital logic design.
Blends academic precision and practical experience in an authoritative introduction to basic principles of digital design and practical requirements. With over 30 years of experience in both industrial and university settings, the author covers the most widespread logic design practices while building a solid foundation of theoretical and engineering principles for students to use as they go forward in this fast moving field.
.
Table of Contents
(NOTE: Most chapters conclude with References, Drill Problems, and Exercises.)
1. Introduction.
About Digital Design. Analog versus Digital. Digital Devices. Electronic Aspects of Digital Design. Software Aspects of Digital Design. Integrated Circuits. Programmable Logic Devices. Application-Specific ICs. Printed-Circuit Boards. Digital-Design Levels. The Name of the Game. Going Forward.
2. Number Systems and Codes.
Positional Number Systems. Octal and Hexadecimal Numbers. General Positional-Number-System Conversions. Addition and Subtraction of Nondecimal Numbers. Representation of Negative Numbers. Two's-Complement Addition and Subtraction. Ones'-Complement Addition and Subtraction. Binary Multiplication. Binary Division. Binary Codes for Decimal Numbers. Gray Code. Character Codes. Codes for Actions, Conditions, and States. n-Cubes and Distance. Codes for Detecting and Correcting Errors. Codes for Serial Data Transmission and Storage.
3. Digital Circuits.
Logic Signals and Gates. Logic Families. CMOS Logic. Electrical Behavior of CMOS Circuits. CMOS Steady-State Electrical Behavior. CMOS Dynamic Electrical Behavior. Other CMOS Input and Output Structures. CMOS Logic Families. Bipolar Logic. Transistor-Transistor Logic. TTL Families. CMOS/TTL Interfacing. Low-Voltage CMOS Logic and Interfacing. Emitter-Coupled Logic.
4. Combinational Logic Design Principles.
Switching Algebra. Combinational-Circuit Analysis. Combinational- Circuit Synthesis. Programmed Minimization Methods. Timing Hazards. The ABEL Hardware Description Language. The VHDL Hardware Description Language.
5. Hardware Description Languages.5.1 HDL-Based Digital Design
5.2 The ABEL Hardware Description Language
5.3 The VHDL Hardware Description Language
5.4 The Verilog Hardware Description Language
6. Combinational Logic Design Practices.
6.1 Documentation Standards
6.2 Circuit Timing
6.3 Combinational PLDs
6.4 Decoders
6.5 Encoders
6.6 Three-State Devices
6.7 Multiplexers
6.8 Exclusive-OR Gates and Parity Circuits
6.9 Comparators
6.10 Adders, Subtractors, and ALUs
6.11 Combinational Multipliers
7. Sequential Logic Design Principles.
Bistable Elements. Latches and Flip-Flops. Clocked Synchronous State-Machine Analysis. Clocked Synchronous State-Machine Design. Designing State Machines Using State Diagrams. State-Machine Synthesis Using Transition Lists. Another State-Machine Design Example. Decomposing State Machines. Feedback Sequential Circuits. Feedback Sequential-Circuit Design. ABEL Sequential-Circuit Design Features. VHDL Sequential-Circuit Design Features.
8. Sequential Logic Design Practices.
Sequential-Circuit Documentation Standards. Latches and Flip-Flops. Sequential PLDs. Counters. Shift Registers. Iterative versus Sequential Circuits. Synchronous Design Methodology. Impediments to Synchronous Design. Synchronizer Failure and Metastability.
9. Memory, CPLDs, and FPGAs.
Read-Only Memory. Read/Write Memory. Static RAM. Dynamic RAM. Complex Programmable Logic Devices. Field-Programmable Gate Arrays.
Index.
商品描述(中文翻譯)
**描述**
適合數位邏輯設計的第一或第二門課程。
本書結合學術精確性與實務經驗,權威性地介紹數位設計的基本原則及實務需求。作者擁有超過30年的工業及大學經驗,涵蓋了最廣泛的邏輯設計實踐,同時為學生建立了理論與工程原則的堅實基礎,以便他們在這個快速變化的領域中繼續前進。
**目錄**
(注意:大多數章節結尾都有參考文獻、練習題和習題。)
1. 介紹。
關於數位設計。類比與數位。數位設備。數位設計的電子方面。數位設計的軟體方面。集成電路。可編程邏輯設備。特定應用集成電路。印刷電路板。數位設計層次。遊戲的名稱。向前邁進。
2. 數字系統與編碼。
位置數字系統。八進制與十六進制數字。一般位置數字系統轉換。非十進制數字的加法與減法。負數的表示。二的補數加法與減法。一的補數加法與減法。二進制乘法。二進制除法。十進制數字的二進制編碼。格雷碼。字符編碼。動作、條件和狀態的編碼。n-立方體與距離。檢測和糾正錯誤的編碼。串行數據傳輸和存儲的編碼。
3. 數位電路。
邏輯信號與邏輯閘。邏輯系列。CMOS邏輯。CMOS電路的電氣行為。CMOS穩態電氣行為。CMOS動態電氣行為。其他CMOS輸入和輸出結構。CMOS邏輯系列。雙極邏輯。晶體管-晶體管邏輯。TTL系列。CMOS/TTL介面。低電壓CMOS邏輯與介面。發射極耦合邏輯。
4. 組合邏輯設計原則。
開關代數。組合電路分析。組合電路綜合。編程最小化方法。時序危險。ABEL硬體描述語言。VHDL硬體描述語言。
5. 硬體描述語言。
5.1 基於HDL的數位設計
5.2 ABEL硬體描述語言
5.3 VHDL硬體描述語言
5.4 Verilog硬體描述語言
6. 組合邏輯設計實踐。
6.1 文件標準
6.2 電路時序
6.3 組合PLD
6.4 解碼器
6.5 編碼器
6.6 三態設備
6.7 多路選擇器
6.8 獨佔或閘與奇偶校驗電路
6.9 比較器
6.10 加法器、減法器與算術邏輯單元(ALU)
6.11 組合乘法器
7. 序列邏輯設計原則。
雙穩態元件。鎖存器與觸發器。時鐘同步狀態機分析。時鐘同步狀態機設計。使用狀態圖設計狀態機。使用轉換列表進行狀態機綜合。另一個狀態機設計範例。狀態機的分解。反饋序列電路。反饋序列電路設計。ABEL序列電路設計特徵。VHDL序列電路設計特徵。
8. 序列邏輯設計實踐。
序列電路文件標準。鎖存器與觸發器。序列PLD。計數器。移位寄存器。迭代電路與序列電路。同步設計方法論。同步設計的障礙。同步器故障與亞穩態。
9. 記憶體、CPLD與FPGA。
只讀記憶體。讀/寫記憶體。靜態隨機存取記憶體(SRAM)。動態隨機存取記憶體(DRAM)。複雜可編程邏輯設備。現場可編程閘陣列(FPGA)。
索引。