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商品描述
This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM.
The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reader with a deep understanding of the major random variation sources, and the characterization of each random variation source. Furthermore, the book presents various CMOS device designs to surmount the random variation in future CMOS technology, emphasizing the applications to SRAM.
商品描述(中文翻譯)
這本書提供了當代互補金屬氧化物半導體（CMOS）裝置設計的綜合概述，描述了如何克服由製程引起的隨機變異，例如邊緣粗糙度（line-edge-roughness）、隨機摻雜波動（random-dopant-fluctuation）和功函數變化（work-function variation），以及新型CMOS裝置在快取記憶體（或靜態隨機存取記憶體，SRAM）中的應用。作者強調了對製程引起的隨機變異的物理理解，以及新型CMOS裝置結構的介紹及其在SRAM中的應用。
本書概述了當前最先進的CMOS技術發展所面臨的技術困境，這是由於在30納米以下技術節點中，晶體管性能受到日益增加的製程引起的隨機/內在變異的影響。因此，對製程引起的隨機/內在變異的物理理解以及解決這些問題的技術方案在新CMOS技術的發展中扮演著關鍵角色。本書旨在讓讀者深入了解主要的隨機變異來源，以及每個隨機變異來源的特徵。此外，本書還展示了各種CMOS裝置設計，以克服未來CMOS技術中的隨機變異，並強調其在SRAM中的應用。
作者簡介
Prof. Changhwan Shin is an Assistant Professor in School of Electrical and Computer Engineering in University of Seoul. Prof. Shin is a graduate of Korea University (BE) and University of California Berkeley (Ph.D). Also, he is Technical Committee Members for IEEE SOI Conference and European Solid-State Device Research Conference (ESSDERC). His research activities cover Electronic Devices and Integrated Circuits; Advanced electronic device architecture for various types of System-on-Chip(SoC) memory and logic devices/ All-in-one Variability Analysis for Nanometer-scale Electronic Devices/ Post-Silicon Technology (CNT, Graphene) & Bio-applications/ Device-and-Circuit Co-optimization: "Low-Level" Digital/Analog Circuit Design Methodology Development/ Programmable Chip Development using Advanced Electronic Devices.
作者簡介(中文翻譯)
申昌煥教授是首爾大學電機與計算機工程學院的助理教授。申教授畢業於高麗大學（BE）和加州大學伯克利分校（Ph.D）。此外，他是IEEE SOI會議和歐洲固態器件研究會議（ESSDERC）的技術委員會成員。他的研究活動涵蓋電子器件和集成電路；針對各類型系統單晶片（System-on-Chip, SoC）記憶體和邏輯器件的先進電子器件架構/納米尺度電子器件的全方位變異分析/後矽技術（CNT、石墨烯）及生物應用/器件與電路的共同優化：“低階”數位/類比電路設計方法論的發展/使用先進電子器件的可編程晶片開發。
