Variation-Aware Analog Structural Synthesis: A Computational Intelligence Approach (Hardcover)
暫譯: 變異感知的類比結構合成：計算智能方法 (精裝本)

McConaghy, Trent, Palmers, Pieter, Peng, Gao

Variation-Aware Analog Structural Synthesis: A Computational Intelligence Approach (Hardcover)
  • 出版商: Springer
  • 出版日期: 2009-07-21
  • 售價: $6,890
  • 貴賓價: 9.5 折 $6,546
  • 語言: 英文
  • 頁數: 305
  • 裝訂: Hardcover - also called cloth, retail trade, or trade
  • ISBN: 9048129052
  • ISBN-13: 9789048129058

    • 海外代購書籍(需單獨結帳)

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Preface. Acronyms and Notation. 1. INTRODUCTION. 1.1 Motivation. 1.2 Background and Contributions to Analog CAD. 1.3 Background and Contributions to AI. 1.4 Analog CAD Is a Fruitfly for AI. 1.5 Conclusion. 2. VARIATION-AWARE SIZING: BACKGROUND. 2.1 Introduction and Problem Formulation. 2.2 Review of Yield Optimization Approaches. 2.3 Conclusion. 3. GLOBALLY RELIABLE, VARIATION-AWARE SIZING: SANGRIA. 3.1 Introduction. 3.2 Foundations: Model-Building Optimization (MBO). 3.3 Foundations: Stochastic Gradient Boosting. 3.4 Foundations: Homotopy. 3.5 SANGRIA Algorithm. 3.6 SANGRIA Experimental Results. 3.7 On Scaling to Larger Circuits. 3.8 Conclusion. 4. KNOWLEDGE EXTRACTION IN SIZING: CAFFEINE. 4.1 Introduction and Problem Formulation. 4.2 Background: GP and Symbolic Regression. 4.3 CAFFEINE Canonical Form Functions. 4.4 CAFFEINE Search Algorithm. 4.5 CAFFEINE Results. 4.6 Scaling Up CAFFEINE: Algorithm. 4.7 Scaling Up CAFFEINE: Results. 4.8 Application: Behaviorial Modeling. 4.9 Application: Process-Variable Robustness Modeling. 4.10 Application: Design-Variable Robustness Modeling. 4.11 Application: Automated Sizing. 4.12 Application: Analytical Performance Tradeoffs. 4.13 Sensitivity To Search Algorithm. 4.14 Conclusion. 5. CIRCUIT TOPOLOGY SYNTHESIS: BACKGROUND. 5.1 Introduction. 5.2 Topology-Centric Flows. 5.3 Reconciling System-Level Design. 5.4 Requirements for a Topology Selection / Design Tool. 5.5 Open-Ended Synthesis and the Analog Problem Domain. 5.6 Conclusion. 6. TRUSTWORTHY TOPOLOGY SYNTHESIS: MOJITO SEARCH SPACE. 6.1 Introduction. 6.2 Search Space Framework. 6.3 A Highly Searchable Op Amp Library. 6.4 Operating-Point Driven Formulation. 6.5 Worked Example. 6.6 Size of Search Space. 6.7 Conclusion. 7. TRUSTWORTHY TOPOLOGY SYNTHESIS: MOJITO ALGORITHM. 7.1 Introduction. 7.2 High-Level Algorithm. 7.3 Search Operators. 7.4 Handling Multiple Objectives. 7.5 Generation of Initial Individuals. 7.6 Experimental Setup. 7.7 Experiment: Hit Target Topologies? 7.8 Experiment: Diversity? 7.9 Experiment: Human-Competitive Results? 7.10 Discussion: Comparison to Open-Ended Structural Synthesis. 7.11 Conclusion. 8. KNOWLEDGE EXTRACTION IN TOPOLOGY SYNTHESIS. 8.1 Introduction. 8.2 Generation of Database. 8.3 Extraction of Specs-To-Topology Decision Tree. 8.4 Global Nonlinear Sensitivity Analysis. 8.5 Extraction of Analytical Performance Tradeoffs. 8.6 Conclusion. 9. VARIATION-AWARE TOPOLOGY SYNTHESIS & KNOWLEDGE EXTRACTION. 9.1 Introduction. 9.2 Problem Specification. 9.3 Background. 9.4 Towards a Solution. 9.5 Proposed Approach: MOJITO-R. 9.6 MOJITO-R Experimental Validation. 9.7 Conclusion. 10. NOVEL VARIATION-AWARE TOPOLOGY SYNTHESIS. 10.1 Introduction. 10.2 Background. 10.3 MOJITO-N Algorithm and Results. 10.4 ISCLEs Algorithm And Results. 10.5 Conclusion. 11. CONCLUSION. 11.1 General Contributions. 11.2 Specific Contributions. 11.3 Future Work. 11.4 Final Remarks. References. Index.

商品描述(中文翻譯)

前言。縮寫與符號。1. 引言。1.1 動機。1.2 類比 CAD 的背景與貢獻。1.3 人工智慧的背景與貢獻。1.4 類比 CAD 是人工智慧的果蠅。1.5 結論。2. 考慮變異的尺寸設計：背景。2.1 引言與問題定義。2.2 產量優化方法回顧。2.3 結論。3. 全球可靠的考慮變異的尺寸設計：SANGRIA。3.1 引言。3.2 基礎：模型建構優化 (MBO)。3.3 基礎：隨機梯度提升。3.4 基礎：同倫法。3.5 SANGRIA 演算法。3.6 SANGRIA 實驗結果。3.7 擴展到更大電路的考量。3.8 結論。4. 尺寸設計中的知識提取：CAFFEINE。4.1 引言與問題定義。4.2 背景：GP 與符號回歸。4.3 CAFFEINE 標準形式函數。4.4 CAFFEINE 搜尋演算法。4.5 CAFFEINE 結果。4.6 擴展 CAFFEINE：演算法。4.7 擴展 CAFFEINE：結果。4.8 應用：行為建模。4.9 應用：過程變數的穩健性建模。4.10 應用：設計變數的穩健性建模。4.11 應用：自動尺寸設計。4.12 應用：分析性能權衡。4.13 對搜尋演算法的敏感性。4.14 結論。5. 電路拓撲合成：背景。5.1 引言。5.2 以拓撲為中心的流程。5.3 調和系統級設計。5.4 拓撲選擇/設計工具的需求。5.5 開放式合成與類比問題領域。5.6 結論。6. 可信的拓撲合成：MOJITO 搜尋空間。6.1 引言。6.2 搜尋空間框架。6.3 高度可搜尋的運算放大器庫。6.4 驅動操作點的公式。6.5 實作範例。6.6 搜尋空間的大小。6.7 結論。7. 可信的拓撲合成：MOJITO 演算法。7.1 引言。7.2 高階演算法。7.3 搜尋運算子。7.4 處理多重目標。7.5 初始個體的生成。7.6 實驗設置。7.7 實驗：是否命中目標拓撲？7.8 實驗：多樣性？7.9 實驗：人類競爭結果？7.10 討論：與開放式結構合成的比較。7.11 結論。8. 拓撲合成中的知識提取。8.1 引言。8.2 數據庫的生成。8.3 規格到拓撲決策樹的提取。8.4 全球非線性敏感度分析。8.5 分析性能權衡的提取。8.6 結論。9. 考慮變異的拓撲合成與知識提取。9.1 引言。9.2 問題規範。9.3 背景。9.4 朝向解決方案。9.5 提議的方法：MOJITO-R。9.6 MOJITO-R 實驗驗證。9.7 結論。10. 新穎的考慮變異的拓撲合成。10.1 引言。10.2 背景。10.3 MOJITO-N 演算法與結果。10.4 ISCLEs 演算法與結果。10.5 結論。11. 結論。11.1 一般貢獻。11.2 特定貢獻。11.3 未來工作。11.4 最後的評論。參考文獻。索引。

作者簡介

Trent McConaghy is co-founder and Chief Scientific Officer of Solido Design Automation Inc. He was a co-founder and Chief Scientist of Analog Design Automation Inc., which was acquired by Synopsys Inc. in 2004. Prior to that, he did research for the Canadian Department of National Defense. He received his PhD degree in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 2008. He received a Bachelor's in Engineering (with great distinction), and a Bachelor's in Computer Science (with great distinction), both from the University of Saskatchewan, Canada, in 1999. He has about 40 peer-reviewed technical papers and patents granted / pending. He has given invited talks / tutorials at many labs, universities, and conferences such as JPL, MIT, ICCAD, and DAC. He is regularly a technical program committee member and reviewer in both the CAD and intelligent systems fields, such as IEEE Trans CAD, ACM TODAES, Electronics Letters, to IEEE Trans Evolutionary Computation, the Journal of Genetic Programming and Evolvable Machines, GPTP, GECCO, ICES, etc. His research interest is in statistical machine learning and intelligent systems, with transistor-level CAD applications such as variation-aware design, analog topology design, automated sizing, knowledge extraction, and symbolic modeling.

Michiel Steyaert was born in Aalst, Belgium, in 1959. He received the masters degree in electrical-mechanical engineering and the Ph.D. degree in electronics from the Katholieke Universiteit Leuven (K.U.Leuven), Heverlee, Belgium in 1983 and 1987, respectively. From 1983 to 1986 he obtained an IWNOL fellowship (Belgian National Fundation for Industrial Research) which allowed him to work as a Research Assistant at the Laboratory ESAT at K.U.Leuven. In 1987 he was responsible for several industrial projects in the field of analog micropower circuits at the Laboratory ESAT as an IWONL Project Researcher. In 1988 he was a Visiting Assistant Professor at the University of California, Los Angeles. In 1989 he was appointed by the National Fund of Scientific Research (Belgium) as Research Associate, in 1992 as a Senior Research Associate and in 1996 as a Research Director at the Laboratory ESAT, K.U.Leuven. Between 1989 and 1996 he was also a part-time Associate Professor. He is now a Full Professor at the K.U.Leuven. His current research interests are in high-performance and high-frequency analog integrated circuits for telecommunication systems and analog signal processing. Prof.Steyaert received the 1990 and 2001 European Solid-State Circuits Conference Best Paper Award. He received the 1991 and the 2000 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications. Prof.Steyaert received the 1995 and 1997 IEEE-ISSCC Evening Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award and is currently an IEEE-Fellow.

Georges Gielen received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. He currently is a Full Professor at the Katholieke Universiteit Leuven. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this area, including several European projects (EU, MEDEA, ESA). He has authored or coauthored five books and more than 300 papers in edited books, international journals and conference proceedings. He regularly is a member of the Program Committees of international conferences (DAC, ICCAD, ISCAS, DATE, CICC...), and served as General Chair of the DATE conference in 2006 and of the International Conference on Computer-Aided Design in 2007. He serves regularly as member of editorial boards of international journals (IEEE Transactions on Circuits and Systems, Springer international journal on Analog Integrated Circuits and Signal Processing, Elsevier Integration). He received the 1995 Best Paper Award in the John Wiley international journal on Circuit Theory and Applications, and was the 1997 Laureate of the Belgian Royal Academy on Sciences, Literature and Arts in the discipline of Engineering. He received the 2000 Alcatel Award from the Belgian National Fund of Scientific Research for his innovative research in telecommunications, and won the DATE 2004 Best Paper Award. He is a Fellow of the IEEE, served as elected member of the Board of Governors of the IEEE Circuits And Systems (CAS) society and as chairman of the IEEE Benelux CAS chapter. He served as the President of the IEEE Circuits And Systems (CAS) Society in 2005. He was elected DATE Fellow in 2007, and received the IEEE Computer Society Outstanding Contribution Award and the IEEE Circuits and Systems Society Meritorious Service Award in 2007.

作者簡介(中文翻譯)

Trent McConaghy 是 Solido Design Automation Inc. 的共同創辦人及首席科學官。他曾是 Analog Design Automation Inc. 的共同創辦人及首席科學家，該公司於 2004 年被 Synopsys Inc. 收購。在此之前，他曾為加拿大國防部進行研究。他於 2008 年在比利時的 Katholieke Universiteit Leuven 獲得電機工程博士學位。他於 1999 年在加拿大薩斯喀徹溫大學獲得工程學士（以優異成績）及計算機科學學士（以優異成績）。他擁有約 40 篇經過同行評審的技術論文及已授權/待授權的專利。他曾在許多實驗室、大學及會議上發表受邀演講/教程，如 JPL、MIT、ICCAD 和 DAC。他定期擔任 CAD 和智能系統領域的技術程序委員會成員及審稿人，涉及 IEEE Trans CAD、ACM TODAES、Electronics Letters、IEEE Trans Evolutionary Computation、Journal of Genetic Programming and Evolvable Machines、GPTP、GECCO、ICES 等期刊。他的研究興趣在於統計機器學習和智能系統，並專注於晶體管級 CAD 應用，如考量變異的設計、類比拓撲設計、自動尺寸調整、知識提取和符號建模。

Michiel Steyaert 於 1959 年出生於比利時的 Aalst。他於 1983 年和 1987 年在比利時的 Katholieke Universiteit Leuven (K.U.Leuven) 獲得電機機械工程碩士學位及電子學博士學位。從 1983 年到 1986 年，他獲得 IWNOL 獎學金（比利時國家工業研究基金會），使他能夠在 K.U.Leuven 的 ESAT 實驗室擔任研究助理。1987 年，他作為 IWONL 項目研究員負責 ESAT 實驗室中幾個類比微功率電路的工業項目。1988 年，他在加州大學洛杉磯分校擔任訪問助理教授。1989 年，他被比利時國家科學研究基金會任命為研究助理，1992 年升任高級研究助理，1996 年成為 K.U.Leuven ESAT 實驗室的研究主任。在 1989 年至 1996 年期間，他也擔任兼任副教授。目前，他是 K.U.Leuven 的正教授。他目前的研究興趣在於電信系統和類比信號處理的高性能和高頻類比集成電路。Steyaert 教授於 1990 年和 2001 年獲得歐洲固態電路會議最佳論文獎。他於 1991 年和 2000 年獲得 NFWO Alcatel-Bell-Telephone 獎，以表彰他在電信集成電路方面的創新工作。Steyaert 教授於 1995 年和 1997 年獲得 IEEE-ISSCC 晚間會議獎，1999 年獲得 IEEE 電路與系統學會 Guillemin-Cauer 獎，並且目前是 IEEE Fellow。

Georges Gielen 於 1986 年和 1990 年在比利時的 Katholieke Universiteit Leuven 獲得電機工程碩士和博士學位。他目前是 Katholieke Universiteit Leuven 的正教授。他的研究興趣在於類比和混合信號集成電路的設計，特別是在類比和混合信號 CAD 工具及設計自動化（建模、模擬和符號分析、類比合成、類比佈局生成、類比和混合信號測試）方面。他是多個（工業）研究項目的協調者或合作夥伴，包括幾個歐洲項目（EU、MEDEA、ESA）。他已撰寫或共同撰寫五本書籍及 300 多篇編輯書籍、國際期刊和會議論文。他定期擔任國際會議的程序委員會成員（DAC、ICCAD、ISCAS、DATE、CICC 等），並於 2006 年和 2007 年擔任 DATE 會議及國際計算機輔助設計會議的總主席。他定期擔任國際期刊的編輯委員會成員（IEEE Transactions on Circuits and Systems、Springer 國際期刊 Analog Integrated Circuits and Signal Processing、Elsevier Integration）。他於 1995 年獲得 John Wiley 國際期刊 Circuit Theory and Applications 的最佳論文獎，並於 1997 年獲得比利時皇家科學、文學與藝術學院的工程學科獎。他於 2000 年獲得比利時國家科學研究基金會的 Alcatel 獎，以表彰他在電信領域的創新研究，並於 2004 年獲得 DATE 最佳論文獎。他是 IEEE Fellow，曾擔任 IEEE Circuits And Systems (CAS) 學會的理事會選舉成員及 IEEE Benelux CAS 分會的主席。他於 2005 年擔任 IEEE Circuits And Systems (CAS) 學會的主席。2007 年，他被選為 DATE Fellow，並於 2007 年獲得 IEEE 計算機學會傑出貢獻獎及 IEEE 電路與系統學會優異服務獎。

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