Systemverilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications
暫譯: SystemVerilog 斷言與功能覆蓋：語言、方法論與應用指南
Ashok B. Mehta
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商品描述
This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SystemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification using SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.
This updated second edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures.
- Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;
- Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies;
- Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;
- Explains each concept in a step-by-step fashion and applies it to a practical real life example;
- Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.商品描述(中文翻譯)
這本書提供了一個實用的、以應用為導向的指南，介紹 SystemVerilog Assertions 和 SystemVerilog Functional Coverage 的語言和方法論。讀者將從使用 SystemVerilog Assertions 和 Functional Coverage 進行功能性硬體驗證的逐步方法中受益，這將使他們能夠發現隱藏且難以找到的錯誤，直接指向錯誤的來源，提供一種乾淨且簡單的方式來建模複雜的時序檢查，並客觀地回答「我們是否已經功能性驗證了所有內容」這個問題。這本書由一位專業的 ASIC/SoC/CPU 和 FPGA 設計及驗證的最終用戶撰寫，通過易於理解的範例、模擬日誌和來自真實專案的應用來解釋每個概念。讀者將能夠應對複雜檢查器的建模以進行功能驗證，從而大幅減少設計和除錯的時間。
這本更新的第二版針對 IEEE-1800 (2012) LRM 中發布的最新功能集進行了修訂，包括許多額外的運算子和特性。此外，許多並行 Assertions/Operators 的解釋也得到了增強，增加了更多的範例和圖示。
- 完整涵蓋最新的 IEEE-1800 2012 LRM 語法和語義；
- 涵蓋 SystemVerilog Assertions 和 SystemVerilog Functional Coverage 語言及方法論；
- 提供有關基於 Assertions 的驗證和功能覆蓋方法論的實用範例，包括其內容、方法和原因；
- 以逐步的方式解釋每個概念，並將其應用於實際的真實範例；
- 包含 6 個實用的 LAB，讓讀者能夠將書中解釋的概念付諸實踐。
