相關主題
商品描述
This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SystemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification using SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.
This updated second edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures.
- Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;
- Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies;
- Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;
- Explains each concept in a step-by-step fashion and applies it to a practical real life example;
- Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.商品描述(中文翻譯)
本書提供了一個實踐導向的指南，介紹了SystemVerilog Assertions和SystemVerilog Functional Coverage的語言和方法論。讀者將從逐步進行的功能硬體驗證方法中受益，使用SystemVerilog Assertions和Functional Coverage，這將使他們能夠發現隱藏和難以找到的錯誤，直接指向錯誤的來源，提供一種清晰簡單的方式來建模複雜的時序檢查，並客觀地回答“我們是否已經對所有功能進行了驗證”。本書由ASIC/SoC/CPU和FPGA設計和驗證的專業最終用戶撰寫，通過易於理解的示例、模擬日誌和來自實際項目的應用來解釋每個概念。讀者將能夠處理功能驗證的複雜檢查器建模，從而大大減少設計和調試的時間。
這本更新的第二版涵蓋了IEEE-1800（2012）LRM中最新的功能集，包括許多額外的運算符和功能。此外，許多並發Assertions/Operators的解釋得到了增強，增加了更多的示例和圖形。
- 完整涵蓋了最新的IEEE-1800 2012 LRM語法和語義；
- 同時涵蓋了SystemVerilog Assertions和SystemVerilog Functional Coverage語言和方法論；
- 提供了Assertion Based Verification和Functional Coverage方法論的實際示例，解釋了其背後的原理和方法；
- 以逐步方式解釋每個概念，並將其應用於實際的例子中；
- 包含6個實際的實驗室，讓讀者能夠實踐本書中介紹的概念。
