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商品描述
This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012.
System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.
商品描述(中文翻譯)
這本書是使用 System Verilog Assertions (SVA) 進行硬體設計的斷言基礎驗證的綜合指南。它使讀者能夠通過在模擬測試、覆蓋率收集和形式分析中使用斷言基礎技術來最小化驗證成本。書中詳細描述了 SVA 的所有語言特性，並附有逐步示例，說明如何使用這些特性來構建強大且可重用的屬性集。這本書還展示了 SVA 如何融入更廣泛的 System Verilog 語言，演示了斷言如何與其他 System Verilog 組件互動。對於剛接觸硬體驗證的讀者，書中提供了有關設計模型和行為的性質、如何進行測試以及斷言所扮演的不同角色的一般材料。本書的第二版涵蓋了最近 IEEE 1800-2012 System Verilog 標準所引入的特性，詳細解釋了新的和增強的斷言結構。這本書使 SVA 對硬體設計師、驗證工程師、形式驗證專家和 EDA 工具開發者變得可用且易於接觸。書中包含了多個深度和難度不一的練習，對於學生來說也非常適合作為教材。
