Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS
Noia, Brandon, Chakrabarty, Krishnendu
- 出版商: Springer
- 出版日期: 2013-12-02
- 售價: $4,360
- 貴賓價: 9.5 折 $4,142
- 語言: 英文
- 頁數: 245
- 裝訂: Hardcover - also called cloth, retail trade, or trade
- ISBN: 3319023772
- ISBN-13: 9783319023779
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相關翻譯:
基於TSV的三維堆疊積體電路的可測性設計與測試最佳化技術 (簡中版)
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其他版本:
Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS
相關主題
商品描述
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
作者簡介
Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.