Deep Reinforcement Learning Processor Design for Mobile Applications
暫譯: 移動應用程式的深度強化學習處理器設計

Lee, Juhyoung, Yoo, Hoi-Jun

  • 出版商: Springer
  • 出版日期: 2024-08-17
  • 售價: $3,760
  • 貴賓價: 9.5$3,572
  • 語言: 英文
  • 頁數: 101
  • 裝訂: Quality Paper - also called trade paper
  • ISBN: 3031367952
  • ISBN-13: 9783031367953
  • 相關分類: ReinforcementDeepLearning
  • 海外代購書籍(需單獨結帳)

商品描述

This book discusses the acceleration of deep reinforcement learning (DRL), which may be the next step in the burst success of artificial intelligence (AI). The authors address acceleration systems which enable DRL on area-limited & battery-limited mobile devices. Methods are described that enable DRL optimization at the algorithm-, architecture-, and circuit-levels of abstraction.
  • Enables deep reinforcement learning (DRL) optimization at algorithm-, architecture-, and circuit-levels of abstraction;
  • Includes methodologies that can reduce the high cost of DRL;
  • Uses analysis of computational workload characteristics of DRL in the context of acceleration.

商品描述(中文翻譯)

本書探討深度強化學習(Deep Reinforcement Learning, DRL)的加速,這可能是人工智慧(Artificial Intelligence, AI)爆炸性成功的下一步。作者針對能夠在面積受限和電池受限的行動裝置上實現 DRL 的加速系統進行討論。文中描述了能夠在算法、架構和電路層級進行 DRL 優化的方法。

- 使深度強化學習(DRL)在算法、架構和電路層級進行優化;
- 包含可以降低 DRL 高成本的方法論;
- 在加速的背景下,分析 DRL 的計算工作負載特徵。

作者簡介

Hoi-Jun Yoo is the KAIST ICT Endowed Chair Professor, School of Electrical Engineering, KAIST. He was the VCSEL pioneer in Bell Communications Research at Red Bank, NJ. USA and Manager of DRAM design group at Hyundai Electronics designing from 1M DRAM to 256M SDRAM.

Currently, he is a full professor of Department of Electrical Engineering at KAIST and the director of the System Design Innovation and Application Research Center (SDIA). From 2003 to 2005, he served as the full time Advisor to the Minister of Korean Ministry of Information and Communication for SoC and Next Generation Computing. His current research interests are Bio Inspired IC Design, Network on a Chip, Multimedia SoC design, Wearable Healthcare Systems, and high speed and low power memory. He has published more than 250 papers, and wrote or edited 5 books, "DRAM Design" (1997, Hongneung), "High Performance DRAM"(1999 Hongneung), "Low Power NoC for High Performance SoC Design"(2008, CRC), "Mobile3D Graphics SoC"(2010, Wiley), and "BioMedical CMOS ICs"(Co-editing with Chris Van Hoof, 2010, Springer), and many chapters of books.

Dr. Yoo received Order of Service Merit from Korean government in 2011 for his contribution to Korean memory industry, Scientist/Engineer of this month Award from Ministry of Education, Science and Technology of Korea in 2010, Best Scholarship Awards of KAIST in 2011. He also received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, Best Research of KAIST Award in 2007, and has been co-recipients of ASP-DAC Design Award 2001, Outstanding Design Awards of 2005, 2006, 2007, 2010, 2011, 2014 A-SSCC, Student Design Contest Award of 2007, 2008, 2010, 2011 DAC/ISSCC. He has served as a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He also served as the IEEE SSCS Distinguished Lecturer ('10-'11) and the TPC chairs of ISSCC 2015, ISWC 2010 and A-SSCC 2008. He is an IEEE Fellow.

Juhyoung Lee received a B.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2017, and a Ph.D. degree in electrical engineering from the KAIST in 2023. He interned at Silicon Research, Meta Reality Lab, CA, USA, in 2022. He joined Qualcomm, San Diego, CA, USA, in 2023, as a Senior Graphics ASIC Design Engineer.

His current research interests include energy-efficient multicore architectures/accelerator ASICs/systems design especially focused on artificial intelligence (AI) including deep neural networks, and graphics applications including ray tracing.

作者簡介(中文翻譯)

兪會俊是韓國科學技術院(KAIST)電機工程學院的資訊通信(ICT)講座教授。他曾是美國新澤西州紅銀行貝爾通訊研究所的VCSEL先驅,並擔任現代電子的DRAM設計小組經理,負責從1M DRAM到256M SDRAM的設計。

目前,他是KAIST電機工程系的正教授,並擔任系統設計創新與應用研究中心(SDIA)的主任。從2003年到2005年,他擔任韓國資訊通信部的全職顧問,專注於系統單晶片(SoC)和下一代計算。他目前的研究興趣包括生物啟發的集成電路設計、片上網路(Network on a Chip)、多媒體SoC設計、可穿戴健康系統,以及高速低功耗記憶體。他已發表超過250篇論文,並撰寫或編輯了5本書籍,包括《DRAM設計》(1997年,弘陵)、《高效能DRAM》(1999年,弘陵)、《高效能SoC設計的低功耗NoC》(2008年,CRC)、《Mobile3D圖形SoC》(2010年,Wiley)和《生醫CMOS集成電路》(與Chris Van Hoof共同編輯,2010年,Springer),以及多篇書籍章節。

兪博士於2011年因對韓國記憶體產業的貢獻獲得韓國政府的服務功勳勳章,並於2010年獲得韓國教育科學技術部的本月最佳科學家/工程師獎,2011年獲得KAIST最佳獎學金獎。他還於1994年獲得韓國電子工業協會獎,以表彰他對DRAM技術的貢獻,1995年獲得Hynix發展獎,2002年獲得韓國半導體產業協會獎,2007年獲得KAIST最佳研究獎,並共同獲得2001年ASP-DAC設計獎、2005、2006、2007、2010、2011年傑出設計獎、2014年A-SSCC獎、2007、2008、2010、2011年DAC/ISSCC學生設計比賽獎。他曾擔任ISSCC、VLSI研討會和A-SSCC的執行委員會成員,並於2010至2011年擔任IEEE SSCS傑出講師,以及2015年ISSCC、2010年ISWC和2008年A-SSCC的程序委員會主席。他是IEEE Fellow。

李柱亨於2017年獲得韓國科學技術院(KAIST)電機工程學士學位,並於2023年獲得KAIST電機工程博士學位。他於2022年在美國加州矽谷的Meta Reality Lab實習。2023年,他加入美國加州聖地牙哥的高通(Qualcomm),擔任高級圖形ASIC設計工程師。

他目前的研究興趣包括以人工智慧(AI)為重點的能源效率多核心架構/加速器ASIC/系統設計,特別是深度神經網路,以及包括光線追蹤在內的圖形應用。