On-Chip Training Npu - Algorithm, Architecture and Soc Design

Donghyeon Han (S'17) received the B.S., M.S., and Ph.D. degrees from the school of electrical engineering of Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2017, 2019 and 2023, respectively. He is now the postdoctoral associate at Massachusetts Institute of Technology (MIT).

His current research interests include low-power system-on-chip design, especially focused on on-device deep neural network training accelerators and hardware-friendly deep learning algorithms. His Ph. D research resulted in several publications in ISSCC, SoVC, JSSC, TCAS-I, IEEE Micro, AICAS, Hotchips, and Coolchips.

Hoi-Jun Yoo is the KAIST ICT Endowed Chair Professor, School of Electrical Engineering, KAIST. He was the VCSEL pioneer in Bell Communications Research at Red Bank, NJ. USA and Manager of DRAM design group at Hyundai Electronics designing from 1M DRAM to 256M SDRAM.

Currently, he is a full professor of Department of Electrical Engineering atKAIST and the director of the System Design Innovation and Application Research Center (SDIA). From 2003 to 2005, he served as the full time Advisor to the Minister of Korean Ministry of Information and Communication for SoC and Next Generation Computing. His current research interests are Bio Inspired IC Design, Network on a Chip, Multimedia SoC design, Wearable Healthcare Systems, and high speed and low power memory. He has published more than 250 papers, and wrote or edited 5 books, "DRAM Design"(1997, Hongneung), "High Performance DRAM"(1999 Hongneung), "Low Power NoC for High Performance SoC Design"(2008, CRC), "Mobile 3D Graphics SoC"(2010, Wiley), and "BioMedical CMOS ICs"(Co-editing with Chris Van Hoof, 2010, Springer), and many chapters of books.

Dr. Yoo received Order of Service Merit from Korean government in 2011 for his contribution to Korean memory industry, Scientist/Engineer of this month Award from Ministry of Education, Science and Technology of Korea in 2010, Best Scholarship Awards of KAIST in 2011. He also received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, Best Research of KAIST Award in 2007, and has been co-recipients of ASP-DAC Design Award 2001, Outstanding Design Awards of 2005, 2006, 2007, 2010, 2011, 2014 A-SSCC, Student Design Contest Award of 2007, 2008, 2010, 2011 DAC/ISSCC. He has served as a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He also served as the IEEE SSCS Distinguished Lecturer ('10-'11) and the TPC chairs of ISSCC 2015, ISWC 2010 and A-SSCC 2008. He is an IEEE Fellow.

Donghyeon Han (S'17) 於 2017、2019 和 2023 年分別獲得韓國科學技術院 (KAIST) 電機工程學院的學士、碩士和博士學位。他目前是麻省理工學院 (MIT) 的博士後研究員。

他目前的研究興趣包括低功耗系統單晶片設計，特別專注於設備內深度神經網絡訓練加速器和硬體友好的深度學習算法。他的博士研究在 ISSCC、SoVC、JSSC、TCAS-I、IEEE Micro、AICAS、Hotchips 和 Coolchips 等期刊上發表了多篇論文。

Hoi-Jun Yoo 是 KAIST 電機工程學院的 ICT 傳承講座教授。他曾是美國新澤西州紅銀行的貝爾通訊研究所的 VCSEL 先驅，並擔任現代電子的 DRAM 設計小組經理，負責從 1M DRAM 到 256M SDRAM 的設計。

目前，他是 KAIST 電機工程系的正教授，並擔任系統設計創新與應用研究中心 (SDIA) 的主任。從 2003 年到 2005 年，他擔任韓國資訊通信部部長的全職顧問，專注於 SoC 和下一代計算。他目前的研究興趣包括生物啟發的 IC 設計、片上網路、媒體 SoC 設計、可穿戴健康系統，以及高速和低功耗記憶體。他已發表超過 250 篇論文，並撰寫或編輯了 5 本書，分別是《DRAM Design》(1997, Hongneung)、《High Performance DRAM》(1999, Hongneung)、《Low Power NoC for High Performance SoC Design》(2008, CRC)、《Mobile 3D Graphics SoC》(2010, Wiley) 和《BioMedical CMOS ICs》(與 Chris Van Hoof 共同編輯, 2010, Springer)，以及多篇書籍章節。

Yoo 博士於 2011 年因對韓國記憶體產業的貢獻獲得韓國政府的服務功勳勳章，並於 2010 年獲得韓國教育科學技術部的本月最佳科學家/工程師獎，2011 年獲得 KAIST 的最佳獎學金獎。他還於 1994 年獲得韓國電子工業協會獎，以表彰他對 DRAM 技術的貢獻，1995 年獲得 Hynix 發展獎，2002 年獲得韓國半導體產業協會獎，2007 年獲得 KAIST 最佳研究獎，並共同獲得 2001 年 ASP-DAC 設計獎、2005、2006、2007、2010、2011 年的傑出設計獎、2014 年 A-SSCC 的學生設計比賽獎 (2007、2008、2010、2011 DAC/ISSCC)。他曾擔任 ISSCC、VLSI 研討會和 A-SSCC 的執行委員會成員，並擔任 IEEE SSCS 傑出講者 (2010-2011) 及 ISSCC 2015、ISWC 2010 和 A-SSCC 2008 的程序委員會主席。他是 IEEE Fellow。