Introduction to Systemverilog (Paperback)
暫譯: SystemVerilog 入門 (平裝本)

Mehta, Ashok B.

Introduction to Systemverilog (Paperback)
  • 出版商: Springer
  • 出版日期: 2022-07-08
  • 售價: $3,400
  • 貴賓價: 9.5 折 $3,230
  • 語言: 英文
  • 頁數: 852
  • 裝訂: Quality Paper - also called trade paper
  • ISBN: 3030713210
  • ISBN-13: 9783030713218
  • 相關分類: Verilog
  • 其他版本: Introduction to Systemverilog (Hardcover)

    • 立即出貨

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商品描述

 

This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs.

 

  • Provides comprehensive coverage of the entire IEEE standard SystemVerilog language;
  • Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features;
  • Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online;
  • Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs.

This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have!

The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers.

 

Mark Glasser

Cerebras Systems

 

 

商品描述(中文翻譯)

這本書提供了一個實用的、以應用為導向的指南，涵蓋整個 IEEE 標準 1800 SystemVerilog 語言。讀者將受益於逐步學習語言及其方法論的細微差別，這將使他們能夠設計和驗證複雜的 ASIC/SoC 和 CPU 晶片。作者涵蓋了語言的整個範疇，包括隨機約束、SystemVerilog 斷言、功能覆蓋、類別、檢查器、介面和數據類型等語言特性。這本書由一位經驗豐富的 ASIC/SoC/CPU 和 FPGA 設計專業終端用戶撰寫，通過易於理解的範例、模擬日誌和來自真實項目的應用來解釋每個概念。讀者將能夠應對多百萬閘極的 ASIC 設計這一複雜任務。

- 提供對整個 IEEE 標準 SystemVerilog 語言的全面覆蓋；
- 涵蓋重要主題，如受限隨機驗證、SystemVerilog 類別、斷言、功能覆蓋、數據類型、檢查器、介面、過程和程序等語言特性；
- 使用易於理解的範例和模擬日誌；範例可進行模擬，並將在線提供；
- 由一位經驗豐富的 ASIC/SoC/CPU 和 FPGA 設計專業終端用戶撰寫。

這是一部相當全面的作品。撰寫這本書一定花了很長時間。我非常喜歡作者對每個 SystemVerilog 結構進行詳細拆解，並深入討論，包括範例代碼和模擬日誌。例如，有一章專門講解數組，另一章專門講解佇列——這真是太好了！

語言參考手冊（LRM）相當密集，作為學習語言的文本使用起來很困難。這本書在語義上提供了 LRM 無法達到的詳細程度。這是這本書的優勢。這將是一本對於新手用戶非常出色的書籍，同時也是經驗豐富的程序員的便捷參考。

馬克·格拉瑟

Cerebras Systems

作者簡介

Ashok Mehta is an ASIC/CPU design and verification engineer with over 30 years of experience in the semiconductor industry. He has worked at companies such as DEC, Data General, Intel, Applied Micro and TSMC. He was an early member of the Verilog technical subcommittees. He is the holder of 19 US Patents in the field of ASIC and 3DIC design and verification. He is also the author of two popular books, one on SystemVerilog Assertions and Functional Coverage and second on ASIC Functional Design Verification - A guide to technologies and methodologies. His current interest include 3DIC semiconductor design verification, System Level Modeling (Virtual Platform) and verification methodologies in general.

作者簡介(中文翻譯)

Ashok Mehta 是一位擁有超過 30 年半導體產業經驗的 ASIC/CPU 設計與驗證工程師。他曾在 DEC、Data General、Intel、Applied Micro 和 TSMC 等公司工作。他是 Verilog 技術小組的早期成員之一。他在 ASIC 和 3DIC 設計與驗證領域擁有 19 項美國專利。他也是兩本熱門書籍的作者，一本是關於 SystemVerilog 斷言與功能覆蓋，第二本則是關於 ASIC 功能設計驗證的指南，涵蓋技術與方法論。他目前的興趣包括 3DIC 半導體設計驗證、系統級建模（虛擬平台）以及一般的驗證方法論。

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