A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof
暫譯: 具作業系統支援的管線式多核心機器：硬體實現與正確性證明

Lutsyk, Petro, Oberhauser, Jonas, Paul, Wolfgang J.

A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof
  • 出版商: Springer
  • 出版日期: 2020-05-10
  • 售價: $2,420
  • 貴賓價: 9.5 折 $2,299
  • 語言: 英文
  • 頁數: 628
  • 裝訂: Quality Paper - also called trade paper
  • ISBN: 3030432424
  • ISBN-13: 9783030432423

    • 海外代購書籍(需單獨結帳)

商品描述

This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. M ller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

- MIPS instruction set architecture (ISA) for application and for system programming

- cache coherent memory system

- store buffers in front of the data caches

- interrupts and exceptions

- memory management units (MMUs)

- pipelined processors: the classical 5 stage pipeline is extended by two pipeline

stages for address translation

- local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

- I/O-interrupt controller and a disk

商品描述(中文翻譯)

這項工作基於 M. Kovalev、S.M. M ller 和 W.J. Paul 於 2014 年出版的書籍《A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness》（LNCS 9000）的結果。

它在閘級層面上展示了一個具有管線處理器和廣泛作業系統支援的多核心機器的建構與正確性證明，具備以下特點：

- MIPS 指令集架構 (ISA) 用於應用程式和系統程式設計
- 快取一致性記憶體系統
- 數據快取前的儲存緩衝區
- 中斷和例外
- 記憶體管理單元 (MMUs)
- 管線處理器：經典的五級管線擴展了兩個用於地址轉換的管線階段
- 支援處理器間中斷 (IPIs) 的本地中斷控制器 (ICs)
- I/O 中斷控制器和磁碟

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