Plasma Etching Processes for Interconnect Realization in VLSI (Hardcover)
暫譯: VLSI 互連實現的等離子蝕刻工藝 (精裝版)

Nicolas Posseme

  • 出版商: Morgan Kaufmann
  • 出版日期: 2015-04-08
  • 售價: $5,190
  • 貴賓價: 9.5$4,931
  • 語言: 英文
  • 頁數: 128
  • 裝訂: Hardcover
  • ISBN: 1785480154
  • ISBN-13: 9781785480157
  • 相關分類: VLSI
  • 海外代購書籍(需單獨結帳)

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商品描述

This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions.

This book focuses on back end of line (BEOL) for high performance device realization and presents an overview of all etch challenges for interconnect realization as well as the current etch solutions proposed in the semiconductor industry. The choice of copper/low-k interconnect architecture is one of the keys for integrated circuit performance, process manufacturability and scalability.

Today, implementation of porous low-k material is mandatory in order to minimize signal propagation delay in interconnections. In this context, the traditional plasma process issues (plasma-induced damage, dimension and profile control, selectivity) and new emerging challenges (residue formation, dielectric wiggling) are critical points of research in order to control the reliability and reduce defects in interconnects. These issues and potential solutions are illustrated by the authors through different process architectures available in the semiconductor industry (metallic or organic hard mask strategies).

  • Presents the difficulties encountered for interconnect realization in very large-scale integrated (VLSI) circuits
  • Focused on plasma-dielectric surface interaction
  • Helps you further reduce the dielectric constant for the future technological nodes

商品描述(中文翻譯)

這是兩本書中的第一本,介紹微電子學中等離子蝕刻過程的挑戰和未來前景,回顧蝕刻過程的過去、現在和未來問題,以便通過創新解決方案來增進對這些問題的理解。

本書專注於高性能設備實現的後端工藝(back end of line, BEOL),並概述了互連實現的所有蝕刻挑戰以及半導體產業中提出的當前蝕刻解決方案。銅/低介電常數(low-k)互連架構的選擇是集成電路性能、製程可製造性和可擴展性的關鍵之一。

如今,實施多孔低介電常數材料是必須的,以最小化互連中的信號傳播延遲。在這個背景下,傳統的等離子過程問題(等離子誘導損傷、尺寸和輪廓控制、選擇性)以及新出現的挑戰(殘留物形成、介電材料波動)是控制可靠性和減少互連缺陷的關鍵研究點。這些問題和潛在解決方案由作者通過半導體產業中可用的不同工藝架構(金屬或有機硬掩模策略)進行說明。

- 提出在超大規模集成(very large-scale integrated, VLSI)電路中實現互連所遇到的困難
- 專注於等離子體-介電表面相互作用
- 幫助您進一步降低未來技術節點的介電常數

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