Index Generation Functions

Sasao, Tsutomu, Thornton, Mitchell a.

Index Generation Functions
  • 出版商: Morgan & Claypool
  • 出版日期: 2019-10-24
  • 售價: $3,150
  • 貴賓價: 9.5 折 $2,993
  • 語言: 英文
  • 頁數: 183
  • 裝訂: Hardcover - also called cloth, retail trade, or trade
  • ISBN: 1681736772
  • ISBN-13: 9781681736778

    • 海外代購書籍(需單獨結帳)

相關主題

商品描述

Index generation functions are binary-input integer valued functions.

They represent functions of content addressable memories (CAMs). Applications include: IP address tables; terminal controllers; URL lists; computer virus scanning circuits; memory patch circuits; list of English words; code converters; and pattern matching circuits.

This book shows memory-based realization of index generation functions. It shows:

  1. methods to implement index generation functions by look-up table (LUT) cascades and index generation units (IGU),
  2. methods to reduce the number of variables using linear transformations, and
  3. methods to estimate the sizes of memories,

with many illustrations, tables, examples, exercises, and their solutions.

作者簡介

Tsutomu Sasao received B.E., M.E., and Ph.D. degrees in Electronics Engineering from Osaka University, Osaka Japan, in 1972, 1974, and 1977, respectively. He has held faculty/research positions at Osaka University, Japan; IBM T. J. Watson Research Center, Yorktown Height, NY; the Naval Postgraduate School, Monterey, CA; and Kyushu Institute of Technology, Iizuka, Japan. Now, he is a Professor of Department of Computer Science, Meiji University, Kawasaki, Japan. His research areas include logic design and switching theory, representations of logic functions, and multiple-valued logic. He has published more than 10 books on logic design including, Logic Synthesis and Optimization (1993), Representation of Discrete Functions (1996), Switching Theory for Logic Synthesis (1999), Logic Synthesis and Verification (2002), Progress in Applications of Boolean Functions (2010), Memory-Based Logic Synthesis (2011), and Applications of Zero-suppressed Decision Diagrams (2015).

He has served Program Chairman for the IEEE International Symposium on Multiple-Valued Logic (ISMVL) many times. Also, he was the Symposium Chairman of the 28th ISMVL held in Fukuoka, Japan in 1998. He received the NIWA Memorial Award in 1979, Takeda Techno-Entrepreneurship Award in 2001, and Distinctive Contribution Awards from IEEE Computer Society MVL-TC for papers presented at ISMVLs in 1986, 1996, 2003, 2004, 2013, and 2018. He has served an associate editor of the IEEE Transactions on Computers. He is a Life Fellow of the IEEE.

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