Readings in Computer Architecture (Paperback)
暫譯: 計算機架構讀本 (平裝本)

Thanks to the continued exponential advances in semiconductor design and the demands of evolving and emerging application domains, the field of computer architecture has never been more dynamic. This, the first major book of computer architecture readings in over two decades, captures this dynamism and reveals Computer Architecture's rich history of practice.

This is much more than a simple collection of papers. The editors have carefully selected the most influential primary sources in specific areas of inquiry that, taken together, present the critical issues of the entire discipline. These include issues in technology, implementation, economics, evaluation methods, instruction set design, instruction level parallelism, dataflow/multithreading, memory systems, input/output systems, single-instruction multiple data parallelism, and multiple-instruction multiple data parallelism. In addition, youll find the editors' thoughtful, focused introductions to each area, providing the context and background necessary for understanding the significance and lasting impact of these papers.

The primary sources and insightful commentary contained in this book provide foundational knowledge for computer architects as well as for those who design supporting system software and compilers. This is an excellent resource for practitioners, instructors, students, and researchers.

Authors:

Mark D. Hill is Professor and Romnes Fellow in the Computer Sciences and Electrical and Computer Engineering departments at the University of Wisconsin-Madison. His research targets the memory systems of shared-memory multiprocessors and high-performance uniprocessors. Much of his recent work was part of the Wisconsin Wind Tunnel project, which examined supporting multiple parallel programming models on hardware ranging from tightly-coupled multiprocessors to clusters of workstations.

Norman P. Jouppi is Consulting Engineer at Compaq Computer Corporations Western Research Laboratory (WRL). Formerly a consulting associate professor in the Department of Electrical Engineering at Stanford University, he has been a key contributor to the architecture and implementation of advanced graphics accelerators (including Neon), the MultiTitan and BIPS microprocessors at WRL, and the MIPS Stanford microprocessor.

Gurindar S. Sohi, a Professor in the Computer Sciences and Electrical and Computer Engineering departments of the University of Wisconsin-Madison, was awarded the 1999 ACM SIGARCH Maurice Wilkes award for contributions in the areas of high issue rate processors and instruction level parallelism. His research has focused on architectural and microarchitectural techniques for high-performance microprocessors.

Table of Contents:

Chapter 1 - Classic Machines: Technology, Implementation, and Economics
Chapter 2 - Methods
Chapter 3 - Instruction Sets
Chapter 4 - Instruction Level Parallelism (ILP)
Chapter 5 - Dataflow and Multithreading
Chapter 6 - Memory Systems
Chapter 7 - I/O: Storage Systems, Networks, and Graphics
Chapter 8 - Single-Instruction Multiple Data (SIMD) Parallelism
Chapter 9 - Multiprocessors and Multicomputers
Chapter 10 - Recent Implementations and Future Prospects

Web-Enhanced:

• Web component (Version 2, August 8, 2000): Provides pointers to 80 additional papers and Web resources (e.g., benchmark sites). Modeled after the book, the ten sections of this Web page follow the ten chapters of the Reader. Each section is preceded by original, introductory text to put the papers and resources in context with each other and with current work. This Web component will be updated annually.
• Web component archives

Related Titles:

Computer Architecture & Design