VLSI Test Principles and Architectures: Design for Testability (Paperback)
暫譯: VLSI 測試原則與架構:可測試性設計 (平裝本)
Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
- 出版商: Morgan Kaufmann
- 出版日期: 2006-07-21
- 售價: $3,350
- 貴賓價: 9.5 折 $3,183
- 語言: 英文
- 頁數: 808
- 裝訂: Paperback
- ISBN: 1493300865
- ISBN-13: 9781493300860
-
相關分類:
VLSI
-
其他版本:
VLSI Test Principles and Architectures: Design for Testability (Hardcover)
商品描述
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
· Most up-to-date coverage of design for testability.
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
商品描述(中文翻譯)
這本書是一本全面的指南,介紹新的設計可測試性(DFT)方法,將向讀者展示如何設計一個可測試且高品質的產品,降低測試成本,提高產品質量和良率,加快上市時間和量產時間。
・最新的設計可測試性覆蓋內容。
・涵蓋在商業DFT工具中常見的行業實踐,但在其他書籍中未有討論。
・每章中都有大量實用的範例,說明基本的VLSI測試原則和DFT架構。
・所有章節的講義幻燈片和練習解答現在均可獲得。
・講師也可以從手冊網站下載PPT幻燈片檔案和MSWORD解答檔案。