Digital VLSI Design and Simulation with Verilog (Hardcover)
暫譯: 數位 VLSI 設計與 Verilog 模擬 (精裝版)
Lata Tripathi, Suman, Saxena, Sobhit, Sinha, Sanjeet K.
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商品描述
Master digital design with VLSI and Verilog using this up-to-date and comprehensive resource from leaders in the field
Digital VLSI Design Problems and Solution with Verilog delivers an expertly crafted treatment of the fundamental concepts of digital design and digital design verification with Verilog HDL. The book includes the foundational knowledge that is crucial for beginners to grasp, along with more advanced coverage suitable for research students working in the area of VLSI design. Including digital design information from the switch level to FPGA-based implementation using hardware description language (HDL), the distinguished authors have created a one-stop resource for anyone in the field of VLSI design.
Through eleven insightful chapters, youÂll learn the concepts behind digital circuit design, including combinational and sequential circuit design fundamentals based on Boolean algebra. YouÂll also discover comprehensive treatments of topics like logic functionality of complex digital circuits with Verilog, using software simulators like ISim of Xilinx. The distinguished authors have included additional topics as well, like:
- A discussion of programming techniques in Verilog, including gate level modeling, model instantiation, dataflow modeling, and behavioral modeling
- A treatment of programmable and reconfigurable devices, including logic synthesis, introduction of PLDs, and the basics of FPGA architecture
- An introduction to System Verilog, including its distinct features and a comparison of Verilog with System Verilog
- A project based on Verilog HDLs, with real-time examples implemented using Verilog code on an FPGA board
Perfect for undergraduate and graduate students in electronics engineering and computer science engineering, Digital VLSI Design Problems and Solution with Verilogalso has a place on the bookshelves of academic researchers and private industry professionals in these fields.
商品描述(中文翻譯)
掌握數位設計,使用 VLSI 和 Verilog,這是來自該領域領導者的最新綜合資源
數位 VLSI 設計問題與解決方案:使用 Verilog 提供了對數位設計和數位設計驗證基本概念的專業處理,使用 Verilog HDL。本書包含了對初學者至關重要的基礎知識,以及適合從事 VLSI 設計研究的進階內容。涵蓋從開關層級到基於 FPGA 的實現的數位設計資訊,這些傑出的作者為 VLSI 設計領域的任何人創建了一個一站式資源。
透過十一個深入的章節,您將學習數位電路設計背後的概念,包括基於布林代數的組合電路和時序電路設計基礎。您還將發現有關複雜數位電路邏輯功能的全面處理,使用 Xilinx 的 ISim 等軟體模擬器。這些傑出的作者還包括了其他主題,例如:
- 在 Verilog 中的程式設計技術討論,包括閘級建模、模型實例化、資料流建模和行為建模
- 可程式化和可重構設備的處理,包括邏輯合成、PLD 的介紹和 FPGA 架構的基本知識
- System Verilog 的介紹,包括其獨特特性以及 Verilog 與 System Verilog 的比較
- 基於 Verilog HDL 的專案,使用 Verilog 代碼在 FPGA 板上實現的實時範例
非常適合電子工程和計算機科學工程的本科生和研究生,數位 VLSI 設計問題與解決方案:使用 Verilog 也適合這些領域的學術研究人員和私營行業專業人士的書架。
作者簡介
Suman Lata Tripathi is Professor of VLSI Design at Lovely Professional University, India. She is a senior member of the IEEE and received her PhD in microelectronics and VLSI Design from Motilal Nehru National Institute of Technology, Allahabad, India.
Sobhit Saxena is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from IIT Roorkee, India.
Sanjeet K. Sinha, PhD, is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from the National Institute of Technology, Silchar, India.
Govind S. Patel, PhD, is Professor of VLSI Design at IIMT College of Engineering, Greater Noida, UP, India. He received his doctorate from Thapar University in Patiala, India.
作者簡介(中文翻譯)
Suman Lata Tripathi 是印度Lovely Professional University的VLSI設計教授。她是IEEE的資深會員,並在印度阿拉哈巴德的Motilal Nehru National Institute of Technology獲得微電子學和VLSI設計的博士學位。
Sobhit Saxena 是印度Lovely Professional University的VLSI設計副教授。他在印度IIT Roorkee獲得博士學位。
Sanjeet K. Sinha, PhD, 是印度Lovely Professional University的VLSI設計副教授。他在印度Silchar的國立技術學院獲得博士學位。
Govind S. Patel, PhD, 是印度Greater Noida的IIMT College of Engineering的VLSI設計教授。他在印度Patiala的Thapar University獲得博士學位。