MOS Devices for Low-Voltage and Low-Energy Applications (Hardcover)
暫譯: 低電壓與低能耗應用的MOS元件 (精裝版)
Yasuhisa Omura, Abhijit Mallik, Naoto Matsuo
- 出版商: Wiley
- 出版日期: 2017-03-12
- 售價: $1,960
- 貴賓價: 9.8 折 $1,921
- 語言: 英文
- 頁數: 496
- 裝訂: Hardcover
- ISBN: 1119107350
- ISBN-13: 9781119107354
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<內容簡介>
Helps readers understand the physics behind MOS devices for low-voltage and low-energy applications
‧ Based on timely published and unpublished work written by expert authors
‧ Discusses various promising MOS devices applicable to low-energy environmental and biomedical uses
‧ Describes the physical effects (quantum, tunneling) of MOS devices
‧ Demonstrates the performance of devices, helping readers to choose right devices applicable to an industrial or consumer environment
‧ Addresses some Ge-based devices and other compound-material-based devices for high-frequency applications and future development of high performance devices.
'Seemingly innocuous everyday devices such as smartphones, tablets and services such as on-line gaming or internet keyword searches consume vast amounts of energy. Even when in standby mode, all these devices consume energy. The upcoming “Internet of Things” (IoT) is expected to deploy 60 billion electronic devices spread out in our homes, cars and cities.
Britain is already consuming up to 16 per cent of all its power through internet use and this rate is doubling every four years. According to The UK’s Daily Mail May (2015), if usage rates continue, all of Britain's power supply could be consumed by internet use in just 20 years. In 2013, U.S. data centers consumed an estimated 91 billion kilowatt-hours of electricity, corresponding to the power generated by seventeen 1000-megawatt nuclear power plants. Data center electricity consumption is projected to increase to roughly 140 billion kilowatt-hours annually by 2020, the equivalent annual output of 50 nuclear power plants. (Natural Resources Defense Council, USA, Feb. 2015)
All these examples stress the urgent need for developing electronic devices that consume as little energy as possible. The book “MOS Devices for Low-Voltage and Low-Energy Applications” explores the different transistor options that can be utilized to achieve that goal. It describes in detail the physics and performance of transistors that can be operated at low voltage and consume little power, such as subthreshold operation in bulk transistors, fully depleted SOI devices, tunnel FETs, multigate and gate-all-around MOSFETs. Examples of low-energy circuits making use of these devices are given as well.
<章節目錄>
Preface xv
Acknowledgments xvi
Part I INTRODUCTION TO LOW?VOLTAGE AND LOW?ENERGY DEVICES 1
1 Why Are Low?Voltage and Low?Energy Devices Desired? 3
References 4
2 History of Low?Voltage and Low?Power Devices 5
2.1 Scaling Scheme and Low?Voltage Requests 5
2.2 Silicon?on?Insulator Devices and Real History 8
References 10
3 Performance Prospects of Subthreshold Logic Circuits 12
3.1 Introduction 12
3.2 Subthreshold Logic and its Issues 12
3.3 Is Subthreshold Logic the Best Solution? 13
References 13
Part II SUMMARY OF PHYSICS OF MODERN SEMICONDUCTOR DEVICES 15
4 Overview 17
References 18
5 Bulk MOSFET 19
5.1 Theoretical Basis of Bulk MOSFET Operation 19
5.2 Subthreshold Characteristics: “OFF State” 19
5.2.1 Fundamental Theory 19
5.2.2 Influence of BTBT Current 23
5.2.3 Points to Be Remarked 24
5.3 Post?Threshold Characteristics: “ON State” 24
5.3.1 Fundamental Theory 24
5.3.2 Self?Heating Effects 26
5.3.3 Parasitic Bipolar Effects 27
5.4 Comprehensive Summary of Short?Channel Effects 27
References 28
6 SOI MOSFET 29
6.1 Partially Depleted Silicon?on?Insulator Metal Oxide Semiconductor Field?Effect Transistors 29
6.2 Fully Depleted (FD) SOI MOSFET 30
6.2.1 Subthreshold Characteristics 30
6.2.2 Post?Threshold Characteristics 36
6.2.3 Comprehensive Summary of Short?Channel Effects 41
6.3 Accumulation?Mode (AM) SOI MOSFET 41
6.3.1 Aspects of Device Structure 41
6.3.2 Subthreshold Characteristics 42
6.3.3 Drain Current Component (I) – Body Current (ID,body) 43
6.3.4 Drain Current Component (II) – Surface Accumulation
Layer Current (ID,acc) 45
6.3.5 Optional Discussions on the Accumulation Mode SOI MOSFET 45
6.4 FinFET and Triple?Gate FET 46
6.4.1 Introduction 46
6.4.2 Device Structures and Simulations 46
6.4.3 Results and Discussion 47
6.4.4 Summary 49
6.5 Gate?all?Around MOSFET 50
References 51
7 Tunnel Field?Effect Transistors (TFETs) 53
7.1 Overview 53
7.2 Model of Double?Gate Lateral Tunnel FET and Device Performance Perspective 53
7.2.1 Introduction 53
7.2.2 Device Modeling 54
7.2.3 Numerical Calculation Results and Discussion 61
7.2.4 Summary 65
7.3 Model of Vertical Tunnel FET and Aspects of its Characteristics 65
7.3.1 Introduction 65
7.3.2 Device Structure and Model Concept 65
7.3.3 Comparing Model Results with TCAD Results 69
7.3.4 Consideration of the Impact of Tunnel Dimensionality on Drivability 72
7.3.5 Summary 75
7.4 Appendix Integration of Eqs. (7.14)–(7.16) 76
References 78
Part III POTENTIAL OF CONVENTIONAL BULK MOSFETs 81
8 Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation 83
8.1 Introduction 83
8.2 Subthreshold Operation and Device Simulation 84
8.3 Model Description 85
8.4 Results 86
8.5 Summary 90
References 90
9 Impact of Halo Doping on the Subthreshold Performance of Deep?Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed?Signal Applications 91
9.1 Introduction 91
9.2 Device Structures and Simulation 92
9.3 Subthreshold Operation 93
9.4 Device Optimization for Subthreshold Analog Operation 95
9.5 Subthreshold Analog Circuit Performance 98
9.6 CMOS Amplifiers with Large Geometry Devices 105
9.7 Summary 106
References 107
10 Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single?Stage CMOS Amplifiers 108
10.1 Introduction 108
10.2 Circuit Description 108
10.3 Device Structure and Simulation 110
10.4 Results and Discussion 110
10.5 PTAT as a Temperature Sensor 116
10.6 Summary 116
References 116
11 Subthreshold Performance of Dual?Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed?Signal Applications 117
11.1 Introduction 117
11.2 Device Structure and Simulation 118
11.3 Results and Discussion 120
11.4 Summary 126
References 127
12 Performance Prospect of Low?Power Bulk MOSFETs 128
Reference 129
Part IV POTENTIAL OF FULLY?DEPLETED SOI MOSFETs 131
13 Demand for High?Performance SOI Devices 133
14 Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology 134
14.1 Introduction 134
14.2 Device Design Concept for 100 nm Gate SOI CMOS 134
14.3 Device Fabrication 136
14.4 Performance of 100?nm? and 85?nm Gate Devices 137
14.4.1 Threshold and Subthreshold Characteristics 137
14.4.2 Drain Current (ID)?Drain Voltage (VD) and ID?Gate Voltage (VG) Characteristics of 100?nm?Gate MOSFET/SIMOX 138
14.4.3 ID–VD and ID–VG Characteristics of 85?nm?Gate MOSFET/SIMOX 142
14.4.4 Switching Performance 142
14.5 Discussion 142
14.5.1 Threshold Voltage Balance in Ultrathin CMOS/SOI Devices 142
14.6 Summary 144
References 145
15 Discussion on Design Feasibility and Prospect of High?Performance Sub?50 nm Channel Single?Gate SOI MOSFET Based on the ITRS Roadmap 147
15.1 Introduction 147
15.2 Device Structure and Simulations 148
15.3 Proposed Model for Minimum Channel Length 149
15.3.1 Minimum Channel Length Model Constructed using Extract A 149
15.3.2 Minimum Channel Length Model Constructed using Extract B 150
15.4 Performance Prospects of Scaled SOI MOSFETs 152
15.4.1 Dynamic Operation Characteristics of Scaled SG SOI MOSFETs 152
15.4.2 Tradeoff and Optimization of Standby Power Consumption and Dynamic Operation 157
15.5 Summary 162
References 162
16 Performance Prospects of Fully Depleted SOI MOSFET?Based Diodes Applied to Schenkel Circuits for RF?ID Chips 164
16.1 Introduction 164
16.2 Remaining Issues with Conventional Schenkel Circuits and an Advanced Proposal 165
16.3 Simulation?Based Consideration of RF Performance of SOI?QD 172
16.4 Summary 176
16.5 Appendix: A Simulation Model for Minority Carrier Lifetime 177
16.6 Appendix: Design Guideline for SOI?QDs 177
References 178
17 The Potential and the Drawbacks of Underlap Single?Gate Ultrathin SOI MOSFET 180
17.1 Introduction 180
17.2 Simulations 181
17.3 Results and Discussion 183
17.3.1 DC Characteristics and Switching Performance: Device A 183
17.3.2 RF Analog Characteristics: Device A 184
17.3.3 Impact of High?κ Gate Dielectric on Performance of USU SOI MOSFET Devices: Devices B and C 185
17.3.4 Impact of Simulation Model on Simulation Results 189
17.4 Summary 192
References 192
18 Practical Source/Drain Diffusion and Body Doping Layouts for High?Performance and Low?Energy Triple?Gate SOI MOSFETs 194
18.1 Introduction 194
18.2 Device Structures and Simulation Model 195
18.3 Results and Discussion 196
18.3.1 Impact of S/D?Underlying Layer on ION, IOFF, and Subthreshold Swing 196
18.3.2 Tradeoff of Short?Channel Effects and Drivability 196
18.4 Summary 201
References 201
19 Gate Field Engineering and Source/Drain Diffusion Engineering for High?Performance Si Wire Gate?All?Around MOSFET and Low?Power Strategy in a Sub?30 nm?Channel Regime 203
19.1 Introduction 203
19.2 Device Structures Assumed and Physical Parameters 204
19.3 Simulation Results and Discussion 206
19.3.1 Performance of Sub?30 nm?Channel Devices and Aspects of Device Characteristics 206
19.3.2 Impact of Cross?Section of Si Wire on Short?Channel Effects and Drivability 212
19.3.3 Minimizing Standby Power Consumption of GAA SOI MOSFET 216
19.3.4 Prospective Switching Speed Performance of GAA SOI MOSFET 217
19.3.5 Parasitic Resistance Issues of GAA Wire MOSFETs 218
19.3.6 Proposal for Possible GAA Wire MOSFET Structure 220
19.4 Summary 221
19.5 Appendix: Brief Description of Physical Models in Simulations 221
References 225
20 Impact of Local High?κ Insulator on Drivability and Standby Power of Gate?All?Around SOI MOSFET 228
20.1 Introduction 228
20.2 Device Structure and Simulations 229
20.3 Results and Discussion 230
20.3.1 Device Characteristics of GAA Devices with Graded?Profile Junctions 230
20.3.2 Device Characteristics of GAA Devices with Abrupt Junctions 235
20.3.3 Behaviors of Drivability and Off?Current 237
20.3.4 Dynamic Performance of Devices with Graded?Profile Junctions 239
20.4 Summary 239
References 240
Part V POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs 241
21 Proposal for Cross?Current Tetrode (XCT) SOI MOSFETs: A 60 dB Single?Stage CMOS Amplifier Using High?Gain Cross?Current Tetrode MOSFET/SIMOX 243
21.1 Introduction 243
21.2 Device Fabrication 244
21.3 Device Characteristics 245
21.4 Performance of CMOS Amplifier 247
21.5 Summary 249
References 249
22 Device Model of the XCT?SOI MOSFET and Scaling Scheme 250
22.1 Introduction 250
22.2 Device Structure and Assumptions for Modeling 251
22.2.1 Device Structure and Features of XCT Device 251
22.2.2 Basic Assumptions for Device Modeling 253
22.2.3 Derivation of Model Equations 254
22.3 Results and Discussion 258
22.3.1 Measured Characteristics of XCT Devices 258
22.4 Design Guidelines 261
22.4.1 Drivability Control 261
22.4.2 Scaling Issues 262
22.4.3 Potentiality of Low?Energy Operation of XCT CMOS Devices 265
22.5 Summary 267
22.6 Appendix: Calculation of MOSFET Channel Current 267
22.7 Appendix: Basic Condition for Drivability Control 271
References 271
23 Low?Power Multivoltage Reference Circuit Using XCT?SOI MOSFET 274
23.1 Introduction 274
23.2 Device Structure and Assumptions for Simulations 274
23.2.1 Device Structure and Features 274
23.2.2 Assumptions for Simulations 277
23.3 Proposal for Voltage Reference Circuits and Simulation Results 278
23.3.1 Two?Reference Voltage Circuit 278
23.3.2 Three?Reference Voltage Circuit 283
23.4 Summary 283
References 284
24 Low?Energy Operation Mechanisms for XCT?SOI CMOS Devices: Prospects for a Sub?20 nm Regime 285
24.1 Introduction 285
24.2 Device Structure and Assumptions for Modeling 286
24.3 Circuit Simulation Results of SOI CMOS and XCT?SOI CMOS 288
24.4 Further Scaling Potential of XCT?SOI MOSFET 291
24.5 Performance Expected from the Scaled XCT?SOI MOSFET 292
24.6 Summary 296
References 296
Part VI QUANTUM EFFECTS AND APPLICATIONS – 1 297
25 Overview 299
References 299
26 Si Resonant Tunneling MOS Transistor 301
26.1 Introduction 301
26.2 Configuration of SRTMOST 302
26.2.1 Structure and Electrostatic Potential 302
26.2.2 Operation Principle and Subthreshold Characteristics 304
26.3 Device Performance of SRTMOST 307
26.3.1 Transistor Characteristics of SRTMOST 307
26.3.2 Logic Circuit Using SRTMOST 310
26.4 Summary 312
References 312
27 Tunneling Dielectric Thin?Film Transistor 314
27.1 Introduction 314
27.2 Fundamental Device Structure 315
27.3 Experiment 315
27.3.1 Experimental Method 315
27.3.2 Calculation Method 317
27.4 Results and Discussion 320
27.4.1 Evaluation of SiNx Film 320
27.4.2 Characteristics of the TDTFT 320
27.4.3 TFT Performance at Low Temperatures 324
27.4.4 TFT Performance at High Temperatures 324
27.4.5 Suppression of the Hump Effect by the TDTFT 330
27.5 Summary 336
References 336
28 Proposal for a Tunnel?Barrier Junction (TBJ) MOSFET 339
28.1 Introduction 339
28.2 Device Structure and Model 339
28.3 Calculation Results 340
28.4 Summary 343
References 343
29 Performance Prediction of SOI Tunneling?Barrier?Junction MOSFET 344
29.1 Introduction 344
29.2 Simulation Model 345
29.3 Simulation Results and Discussion 349
29.3.1 Fundamental Properties of TBJ MOSFET 349
29.3.2 Optimization of Device Parameters and Materials 349
29.4 Summary 357
References 357
30 Physics?Based Model for TBJ?MOSFETs and High?Frequency Performance Prospects 358
30.1 Introduction 358
30.2 Device Structure and Device Model for Simulations 359
30.3 Simulation Results and Discussion 360
30.3.1 Current Drivability 361
30.3.2 Threshold Voltage Issue 362
30.3.3 Subthreshold Characteristics 363
30.3.4 Radio?Frequency Characteristics 363
30.4 Summary 365
References 365
31 Low?Power High?Temperature?Operation?Tolerant (HTOT) SOI MOSFET 367
31.1 Introduction 367
31.2 Device Structure and Simulations 368
31.3 Results and Discussion 371
31.3.1 Room?Temperature Characteristics 371
31.3.2 High?Temperature Characteristics 373
31.4 Summary 377
References 379
Part VII QUANTUM EFFECTS AND APPLICATIONS – 2 381
32 Overview of Tunnel Field?Effect Transistor 383
References 385
33 Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field?Effect Transistor 386
33.1 Introduction 386
33.2 Device Structure and Simulation 387
33.3 Results and Discussion 387
33.3.1 Effects of Variation in the Spacer Dielectric Constant 387
33.3.2 Effects of Variation in the Spacer Width 391
33.3.3 Effects of Variation in the Source Doping Concentration 392
33.3.4 Effects of a Gate?Source Overlap 394
33.3.5 Effects of a Gate?Channel Underlap 394
33.4 Summary 397
References 397
34 The Impact of a Fringing Field on the Device Performance of a P?Channel Tunnel Field?Effect Transistor with a High?κ Gate Dielectric 399
34.1 Introduction 399
34.2 Device Structure and Simulation 399
34.3 Results and Discussion 400
34.3.1 Effects of Variation in the Gate Dielectric Constant 400
34.3.2 Effects of Variation in the Spacer Dielectric Constant 408
34.4 Summary 410
References 410
35 Impact of a Spacer?Drain Overlap on the Characteristics of a Silicon Tunnel Field?Effect Transistor Based on Vertical Tunneling 412
35.1 Introduction 412
35.2 Device Structure and Process Steps 413
35.3 Simulation Setup 414
35.4 Results and Discussion 416
35.4.1 Impact of Variation in the Spacer?Drain Overlap 416
35.4.2 Influence of Drain on the Device Characteristics 424
35.4.3 Impact of Scaling 426
35.5 Summary 429
References 430
36 Gate?on?Germanium Source Tunnel Field?Effect Transistor Enabling Sub?0.5?V Operation 431
36.1 Introduction 431
36.2 Proposed Device Structure 431
36.3 Simulation Setup 432
36.4 Results and Discussion 434
36.4.1 Device Characteristics 434
36.4.2 Effects of Different Structural Parameters 435
36.4.3 Optimization of Different Structural Parameters 436
36.5 Summary 445
References 445
Part VIII PROSPECTS OF LOW?ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS 447
37 Performance Comparison of Modern Devices 449
References 450
38 Emerging Device Technology and the Future of MOSFET 452
38.1 Studies to Realize High?Performance MOSFETs based on Unconventional Materials 452
38.2 Challenging Studies to Realize High?Performance MOSFETs based on the Nonconventional Doctrine 453
References 454
39 How Devices Are and Should Be Applied to Circuits 456
39.1 Past Approach 456
39.2 Latest Studies 456
References 457
40 Prospects for Low?Energy Device Technology and Applications 458
References 459
Bibliography 460
Index 463
商品描述(中文翻譯)
內容簡介
幫助讀者理解低電壓和低能耗應用中MOS器件的物理原理
‧ 基於專家作者撰寫的及時發表和未發表的工作
‧ 討論各種適用於低能耗環境和生物醫學用途的有前景的MOS器件
‧ 描述MOS器件的物理效應（量子、隧道效應）
‧ 演示器件的性能，幫助讀者選擇適用於工業或消費環境的正確器件
‧ 涉及一些基於鍺的器件和其他化合材料基礎的器件，用於高頻應用和未來高性能器件的發展。
看似無害的日常設備，如智能手機、平板電腦以及在線遊戲或互聯網關鍵字搜索等服務，消耗了大量的能源。即使在待機模式下，所有這些設備也會消耗能源。即將到來的「物聯網」（IoT）預計將在我們的家庭、汽車和城市中部署600億個電子設備。
英國目前通過互聯網使用消耗了高達16%的電力，這一比例每四年翻一番。根據《每日郵報》（2015年5月），如果使用率持續上升，英國的所有電力供應在短短20年內可能會被互聯網使用所消耗。2013年，美國數據中心消耗了約910億千瓦時的電力，相當於十七座1000兆瓦核電廠所產生的電力。預計到2020年，數據中心的電力消耗將增至約1400億千瓦時，這相當於50座核電廠的年產量。（美國自然資源保護協會，2015年2月）
所有這些例子強調了開發能耗盡可能低的電子設備的迫切需求。書籍《低電壓和低能耗應用的MOS器件》探討了可以用來實現該目標的不同晶體管選項。它詳細描述了可以在低電壓下運行並消耗少量功率的晶體管的物理和性能，例如在大體積晶體管中的亞閾值操作、完全耗盡的SOI器件、隧道場效應晶體管（Tunnel FETs）、多閘和全閘MOSFET。書中還給出了利用這些器件的低能耗電路的例子。
章節目錄
前言 xv
致謝 xvi
第一部分 低電壓和低能耗器件介紹 1
1 為什麼需要低電壓和低能耗器件？ 3
參考文獻 4
2 低電壓和低功率器件的歷史 5
2.1 縮放方案和低電壓要求 5
2.2 硅絕緣體器件及其真實歷史 8
參考文獻 10
3 亞閾值邏輯電路的性能前景 12
3.1 介紹 12
3.2 亞閾值邏輯及其問題 12
3.3 亞閾值邏輯是最佳解決方案嗎？ 13
參考文獻 13
第二部分 現代半導體器件物理概述 15
4 概述 17
參考文獻 18
5 大體積MOSFET 19
5.1 大體積MOSFET操作的理論基礎 19
5.2 亞閾值特性：「關閉狀態」 19
5.2.1 基本理論 19
5.2.2 BTBT電流的影響 23
5.2.3 需要注意的要點 24
5.3 閾值後特性：「開啟狀態」 24
5.3.1 基本理論 24
5.3.2 自加熱效應 26
5.3.3 寄生雙極效應 27
5.4 短通道效應的綜合總結 27
參考文獻 28
6 SOI MOSFET 29
6.1 部分耗盡的硅絕緣體金屬氧化物半導體場效應晶體管 29
6.2 完全耗盡（FD）SOI MOSFET 30
6.2.1 亞閾值特性 30
6.2.2 閾值後特性 36
6.2.3 短通道效應的綜合總結 41
6.3 積累模式（AM）SOI MOSFET 41
6.3.1 器件結構的各個方面 41
6.3.2 亞閾值特性 42
6.3.3 漏電流組件（I）－體電流（ID,body） 43
6.3.4 漏電流組件（II）－表面積累層電流（ID,acc） 45
6.3.5 積累模式SOI MOSFET的可選討論 45
6.4 FinFET和三閘FET 46
6.4.1 介紹 46
6.4.2 器件結構和模擬 46
6.4.3 結果與討論 47
6.4.4 總結 49
6.5 全閘MOSFET 50
參考文獻 51
7 隧道場效應晶體管（TFETs） 53
7.1 概述 53
7.2 雙閘側隧道FET的模型及器件性能前景 53
7.2.1 介紹 53
7.2.2 器件建模 54
7.2.3 數值計算結果與討論 61
7.2.4 總結 65
7.3 垂直隧道FET的模型及其特性方面 65
7.3.1 介紹 65
7.3.2 器件結構和模型概念 65
7.3.3 將模型結果與TCAD結果進行比較 69
7.3.4 考慮隧道維度對驅動能力的影響 72
7.3.5 總結 75
7.4 附錄 整合方程式（7.14）－（7.16） 76
參考文獻 78
第三部分 傳統大體積MOSFET的潛力 81
8 在亞閾值操作範圍內使用深亞微米MOSFET的類比電路性能評估 83
8.1 介紹 83
8.2 亞閾值操作和器件模擬 84
8.3 模型描述 85
8.4 結果 86
8.5 總結 90
參考文獻 90
9 鳍狀摻雜對深亞微米CMOS器件和電路的亞閾值性能影響，適用於超低功率類比/混合信號應用 91
9.1 介紹 91
9.2 器件結構和模擬 92
9.3 亞閾值操作 93
9.4 亞閾值類比操作的器件優化 95
9.5 亞閾值類比電路性能 98
9.6 大幾何器件的CMOS放大器 105
9.7 總結 106
參考文獻 107
10 深亞微米單級CMOS放大器的亞閾值性能及通道工程的影響研究 108
10.1 介紹 108
10.2 電路描述 108
10.3 器件結構和模擬 110
10.4 結果與討論 110
10.5 PTAT作為溫度傳感器 116
10.6 總結 116
參考文獻 116
11 雙材料閘CMOS器件和電路的亞閾值性能，適用於超低功率類比/混合信號應用 117
11.1 介紹 117
11.2 器件結構和模擬 118
11.3 結果與討論 120
11.4 總結 126
參考文獻 127
12 低功率大體積MOSFET的性能前景 128
參考文獻 129
第四部分 完全耗盡SOI MOSFET的潛力 131
13 對高性能SOI器件的需求 133
14 演示具有薄埋氧化層的100 nm閘SOI CMOS及其對器件技術的影響 134
14.1 介紹 134
14.2 100 nm閘SOI CMOS的器件設計概念 134
14.3 器件製造 136
14.4 100 nm和85 nm閘器件的性能 137
14.4.1 閾值和亞閾值特性 137
14.4.2 漏電流（ID）－漏電壓（VD）和ID－閘電壓（VG）特性 138
14.4.3 ID－VD和ID－VG特性 142
14.4.4 開關性能 142
14.5 討論 142
14.5.1 超薄CMOS/SOI器件中的閾值電壓平衡 142
14.6 總結 144
參考文獻 145
15 基於ITRS路線圖的高性能亞50 nm通道單閘SOI MOSFET的設計可行性和前景討論 147
15.1 介紹 147
15.2 器件結構和模擬 148
15.3 最小通道長度的提議模型 149
15.3.1 使用Extract A構建的最小通道長度模型 149
15.3.2 使用Extract B構建的最小通道長度模型 150
15.4 縮放SOI MOSFET的性能前景 152
15.4.1 縮放SG SOI MOSFET的動態操作特性 152
15.4.2 待機功耗和動態操作的權衡與優化 157
15.5 總結 162
參考文獻 162
16 應用於RF-ID晶片的完全耗盡SOI MOSFET基二極體的性能前景 164
16.1 介紹 164
16.2 傳統Schenkel電路的剩餘問題及其進階提案 165
