Integrated Circuit Design: IC Design Flow and Project-Based Learning

Yang, Xiaokun

Integrated Circuit Design: IC Design Flow and Project-Based Learning
  • 出版商: CRC
  • 出版日期: 2024-11-20
  • 售價: $4,510
  • 貴賓價: 9.5 折 $4,285
  • 語言: 英文
  • 頁數: 464
  • 裝訂: Hardcover - also called cloth, retail trade, or trade
  • ISBN: 1032030798
  • ISBN-13: 9781032030791

    • 海外代購書籍(需單獨結帳)

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商品描述

This textbook seeks to foster a deep understanding of the field by introducing the industry integrated circuit (IC) design flow and offering tape-out or pseudo tape-out projects for hands-on practice, facilitating project-based learning (PBL) experiences.

Integrated Circuit Design: IC Design Flow and Project-Based Learning aims to equip readers for entry-level roles as IC designers in the industry and as hardware design researchers in academia. The book commences with an overview of the industry IC design flow, with a primary focus on register-transfer level (RTL) design, the automation of simulation and verification, and system-on-chip (SoC) integration. To build connections between RTL design and physical hardware, FPGA (field-programmable gate array) synthesis and implementation is utilized to illustrate the hardware description and performance evaluation. The second objective of this book is to provide readers with practical, hands-on experience through tape-out or pseudo tape-out experiments, labs, and projects. These activities are centered on coding format, industry design rules (synthesizable Verilog designs, clock domain crossing, etc.), and commonly-used bus protocols (arbitration, handshaking, etc.), as well as established design methodologies for widely-adopted hardware components, including counters, timers, finite state machines (FSMs), I2C, single/dual-port and ping-pong buffers/register files, FIFOs, floating-point units (FPUs), numerical hardware (Fourier transform, matrix-matrix multiplication, etc.), direct memory access (DMA), image processing designs, neural networks, and more.

The textbook caters to a diverse readership, including junior and senior undergraduate students, as well as graduate students pursuing degrees in electrical engineering, computer engineering, computer science, and related fields. The target audience is expected to have a basic understanding of Boolean Algebra and Karnaugh Maps, as well as prior familiarity with digital logic components such as AND/OR gates, latches, and flip-flops. The book will also be useful for entry-level RTL designers and verification engineers who are embarking on their journey in application-specific IC (ASIC) and FPGA design industry.

商品描述(中文翻譯)

本教科書旨在透過介紹產業整合電路（IC）設計流程，並提供實際的 tape-out 或偽 tape-out 專案以進行實作練習，促進以專案為基礎的學習（PBL）經驗，來培養對該領域的深入理解。

《整合電路設計：IC 設計流程與專案基礎學習》旨在為讀者提供進入產業作為 IC 設計師的入門角色，以及作為學術界硬體設計研究者的能力。本書首先概述產業 IC 設計流程，主要聚焦於寄存器傳輸級（RTL）設計、模擬與驗證的自動化，以及系統單晶片（SoC）整合。為了建立 RTL 設計與實體硬體之間的聯繫，利用 FPGA（現場可程式化閘陣列）合成與實作來說明硬體描述與性能評估。本書的第二個目標是透過 tape-out 或偽 tape-out 實驗、實驗室和專案，為讀者提供實際的動手經驗。這些活動圍繞著編碼格式、產業設計規則（可合成的 Verilog 設計、時鐘域交叉等）以及常用的匯流排協議（仲裁、握手等），以及針對廣泛採用的硬體元件（包括計數器、計時器、有限狀態機（FSM）、I2C、單/雙埠及乒乓緩衝區/寄存器檔、FIFO、浮點運算單元（FPU）、數值硬體（傅立葉變換、矩陣乘法等）、直接記憶體存取（DMA）、影像處理設計、神經網路等）所建立的設計方法論。

本教科書適合多元的讀者群，包括大學三、四年級學生以及攻讀電機工程、計算機工程、計算機科學及相關領域的研究生。目標讀者預期具備基本的布林代數和卡諾圖的理解，以及對數位邏輯元件（如 AND/OR 閘、鎖存器和觸發器）的先前熟悉。本書對於剛開始進入應用特定整合電路（ASIC）和 FPGA 設計產業的入門級 RTL 設計師和驗證工程師也將非常有用。

作者簡介

Dr. Xiaokun Yang currently serves as an Associate Professor at the College of Science and Engineering at the University of Houston Clear Lake, located in Houston, Texas. Additionally, since 2022, he has held the role of Affiliate Faculty at Lawrence Berkeley National Laboratory, situated in Berkeley, California. Dr. Yang earned his Ph.D. in the Department of Electrical and Computer Engineering at Florida International University (FIU) in the spring of 2016. He also brings extensive industry experience, having worked as ASIC Design and Verification Engineer at Advanced Micro Devices (AMD) and China Electronic Corporation (CEC) during 2007-2012. Dr. Yang's research interests center on specialized hardware design and acceleration for future high-performance computing, design automation for numerical hardware and machine learning, and advanced high-performance SoC architecture. As the first author or corresponding author, Dr. Yang has published more than 45 papers including 3 patents, more than 15 peer-review journals, and more than 30 prestigious international conferences. He has served as guest editor and journal reviewers including IEEE Transactions on Computer, IEEE Transactions on VLSI, IEEE Transactions on Education, ACM Transactions on Architecture and Code Optimization, and MDPI Micromachines, and numerous conference committees including ISQED and ISVLSI.

作者簡介(中文翻譯)

目前，楊小坤博士擔任德州休士頓的休士頓清湖大學科學與工程學院的副教授。此外，自2022年以來，他還擔任位於加州伯克利的勞倫斯伯克利國家實驗室的附屬教員。楊博士於2016年春季在佛羅里達國際大學（FIU）的電機與計算機工程系獲得博士學位。他擁有豐富的產業經驗，曾於2007年至2012年在超微半導體（AMD）和中國電子公司（CEC）擔任ASIC設計與驗證工程師。楊博士的研究興趣集中在未來高效能計算的專用硬體設計與加速、數值硬體與機器學習的設計自動化，以及先進的高效能系統單晶片（SoC）架構。作為第一作者或通訊作者，楊博士已發表超過45篇論文，包括3項專利、超過15篇同行評審期刊文章，以及超過30場國際知名會議的論文。他曾擔任多個期刊的客座編輯和審稿人，包括IEEE計算機學報、IEEE VLSI學報、IEEE教育學報、ACM架構與代碼優化學報，以及MDPI微型機器學報，並參與多個會議委員會，包括ISQED和ISVLSI。

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