Verilog by Example: A Concise Introduction for FPGA Design (Paperback)
Blaine Readler
- 出版商: Full Arc Press
- 出版日期: 2011-04-19
- 售價: $1,040
- 貴賓價: 9.5 折 $988
- 語言: 英文
- 頁數: 124
- 裝訂: Paperback
- ISBN: 0983497303
- ISBN-13: 9780983497301
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相關分類:
FPGA、Verilog
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商品描述
A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with "The Elements of Style," VERILOG BY EXAMPLE does for FPGA design.
商品描述(中文翻譯)
這本書是一本實用的入門指南，針對已經熟悉數位設計基礎的學生和實踐工程師，以易於理解的例子逐步介紹了Verilog硬體描述語言的使用。從一個簡單但可行的設計範例開始，逐漸引入了語言的更複雜基礎，直到揭示了Verilog的所有主要功能。內容包括狀態機、模塊化設計、基於FPGA的記憶體、時鐘管理、專用I/O以及模擬技術的介紹。目標是讓讀者能夠設計真實世界的FPGA解決方案。書中使用的所有範例代碼都可以在網上找到。就像Strunk和White在英語語言上所做的那樣，《VERILOG BY EXAMPLE》對於FPGA設計起到了相同的作用。
