Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and PrimeTime, 2/e (Hardcover)
暫譯: 進階ASIC晶片合成:使用Synopsys Design Compiler、Physical Compiler與PrimeTime,第二版(精裝本)

Himanshu Bhatnagar

  • 出版商: Springer
  • 出版日期: 2001-12-31
  • 售價: $9,940
  • 貴賓價: 9.5$9,443
  • 語言: 英文
  • 頁數: 328
  • 裝訂: Hardcover
  • ISBN: 0792376447
  • ISBN-13: 9780792376446
  • 相關分類: Compiler
  • 海外代購書籍(需單獨結帳)

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商品描述

Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.

商品描述(中文翻譯)

《進階 ASIC 晶片合成:使用 Synopsys® Design Compiler®、Physical Compiler® 和 PrimeTime®,第二版》描述了在 ASIC 晶片合成、物理合成、形式驗證和靜態時序分析中使用的先進概念和技術,並使用 Synopsys 工具套件。此外,針對 VDSM(非常深亞微米)技術的整個 ASIC 設計流程方法論也詳細介紹。

本書的重點在於 Synopsys 工具的實時應用,這些工具用於解決在 VDSM 幾何中遇到的各種問題。讀者將接觸到一種有效的設計方法論,以處理複雜的亞微米 ASIC 設計。本書強調 HDL 編碼風格、合成與優化、動態模擬、形式驗證、DFT 掃描插入、佈局連結、物理合成和靜態時序分析。在每個步驟中,識別與設計流程每個階段相關的問題,並詳細描述解決方案和替代方法。此外,與佈局相關的關鍵問題,包括時鐘樹合成和後端整合(佈局連結)也進行了深入討論。此外,本書還包含了針對最佳合成解決方案的 Synopsys 技術庫和 HDL 編碼風格的深入討論。

本書的目標讀者是從事 ASIC 設計的工程師和修讀進階 VLSI 課程的碩士生,專注於 ASIC 晶片設計和 DFT 技術。