Integrated Circuit Manufacturability: The Art Of Process And Design Integration
暫譯: 集成電路可製造性:工藝與設計整合的藝術

Jose Pineda de Gyvez, IEEE Circuits and Systems Society, Dhiraj Pradhan

  • 出版商: Wiley
  • 出版日期: 1998-10-30
  • 售價: $8,810
  • 貴賓價: 9.5$8,370
  • 語言: 英文
  • 頁數: 332
  • 裝訂: Hardcover
  • ISBN: 0780334477
  • ISBN-13: 9780780334472
  • 海外代購書籍(需單獨結帳)

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商品描述

Description:

Electrical Engineering Integrated Circuit Manufacturability The Art of Process and Design Integration Integrated Circuit Manufacturability provides comprehensive coverage of the process and design variables that determine the ease and feasibility of the fabrication (or manufacturability) of contemporary VLSI systems and circuits. This book progresses from semiconductor processing to electrical design to system architecture. The material provides a theoretical background as well as case studies, examining the entire design for the manufacturing path from circuit to silicon. Each chapter includes tutorial and practical applications coverage. Integrated Circuit Manufacturability illustrates the implications of manufacturability at every level of abstraction, including the effects of defects on the layout, their mapping to electrical faults, and the corresponding approaches to detect such faults. The reader will be introduced to key practical issues normally applied in industry and usually required by quality, product, and design engineering departments in today’s design practices:

  • Yield management strategies
  • Effects of spot defects
  • Inductive fault analysis and testing
  • Fault-tolerant architectures and MCM testing strategies

This book will serve design and product engineers both from academia and industry. It can also be used as a reference or textbook for introductory graduate-level courses on manufacturing.

 

Table of Contents:

Preface.

Introduction (José Pineda de Gyvez).

Defect Monitoring and Characterization (Eric Bruls).

Digital CMOS Fault Modeling and Inductive Fault Analysis (Manoj Sachdev).

Functional Yield Modeling (Gary C. Cheek and Geoff O'Donoghue).

Critical Area and Fault Probability Prediction (D.M.H. Walker).

Statistical Methods of Parametric Yield and Quality Enhancement (Maciej Styblinski).

Architectural Fault Tolerance (S.K. Tewksbury).

Design for Test and Manufacturability (Dhiraj Pradhan and Adit Singh).

Testing Solutions for MCM Manufacturing (Yervant Zorian).

Index.

About the Editors.

商品描述(中文翻譯)

**書籍描述:**
《電機工程集成電路可製造性:過程與設計整合的藝術》全面涵蓋了決定當代 VLSI 系統和電路製造(或可製造性)難易度的過程和設計變數。本書從半導體處理進展到電氣設計,再到系統架構。材料提供了理論背景以及案例研究,檢視從電路到矽的整個製造設計路徑。每一章節都包括教程和實用應用的內容。《集成電路可製造性》說明了在每個抽象層級上可製造性的影響,包括缺陷對佈局的影響、它們對電氣故障的映射,以及檢測這些故障的相應方法。讀者將接觸到在業界通常應用的關鍵實務問題,這些問題通常是當今設計實踐中質量、產品和設計工程部門所需的:

- 產量管理策略
- 點缺陷的影響
- 感應故障分析與測試
- 容錯架構與 MCM 測試策略

本書將服務於來自學術界和業界的設計和產品工程師。它也可以作為製造入門研究生課程的參考書或教科書。

**目錄:**
前言
介紹(José Pineda de Gyvez)
缺陷監控與特徵化(Eric Bruls)
數位 CMOS 故障建模與感應故障分析(Manoj Sachdev)
功能產量建模(Gary C. Cheek 和 Geoff O'Donoghue)
關鍵區域與故障概率預測(D.M.H. Walker)
參數產量與質量增強的統計方法(Maciej Styblinski)
架構容錯(S.K. Tewksbury)
測試與可製造性設計(Dhiraj Pradhan 和 Adit Singh)
MCM 製造的測試解決方案(Yervant Zorian)
索引
編輯介紹