Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors [Hardcover]
暫譯: 微處理器架構:從簡單的管線到晶片多處理器【精裝版】

Jean-Loup Baer

  • 出版商: Cambridge
  • 出版日期: 2009-12-07
  • 售價: $3,500
  • 貴賓價: 9.5$3,325
  • 語言: 英文
  • 頁數: 382
  • 裝訂: Hardcover
  • ISBN: 0521769922
  • ISBN-13: 9780521769921
  • 相關分類: Computer-networks
  • 立即出貨 (庫存=1)

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商品描述

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as - the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers - optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations - design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors - state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

商品描述(中文翻譯)

本書全面描述了微處理器的架構,從簡單的順序短管線設計到亂序超標量架構。內容討論了以下主題:
- 亂序處理所需的政策和機制,例如寄存器重命名、保留站和重排序緩衝區
- 提高性能的優化技術,例如分支預測、指令排程和載入-儲存猜測
- 設計選擇和增強措施,以容忍單處理器和多處理器的快取層級延遲
- 最先進的多執行緒和多處理技術,強調單晶片實現

這些主題以概念性想法呈現,並在適當的情況下提供評估性能影響的指標和實現範例。重點在於事物在黑箱和算法層面上的運作方式。作者還提供了足夠的寄存器傳輸層級細節,使讀者能夠理解設計特徵如何增強性能以及複雜性。