Code Design for Dependable Systems: Theory and Practical Applications
暫譯: 可靠系統的程式設計：理論與實務應用
Eiji Fujiwara
- 出版商: Wiley
- 出版日期: 2006-06-01
- 售價: $1,482
- 語言: 英文
- 頁數: 720
- 裝訂: Hardcover
- ISBN: 0471756180
- ISBN-13: 9780471756187
下單後立即進貨 (約5~7天)
相關主題
商品描述
Theoretical and practical tools to master matrix code design strategy and technique
Error correcting and detecting codes are essential to improving system reliability and have popularly been applied to computer systems and communication systems. Coding theory has been studied mainly using the code generator polynomials; hence, the codes are sometimes called polynomial codes. On the other hand, the codes designed by parity check matrices are referred to in this book as matrix codes. This timely book focuses on the design theory for matrix codes and their practical applications for the improvement of system reliability. As the author effectively demonstrates, matrix codes are far more flexible than polynomial codes, as they are capable of expressing various types of code functions.
In contrast to other coding theory publications, this one does not burden its readers with unnecessary polynomial algebra, but rather focuses on the essentials needed to understand and take full advantage of matrix code constructions and designs. Readers are presented with a full array of theoretical and practical tools to master the fine points of matrix code design strategy and technique:
* Code designs are presented in relation to practical applications, such as high-speed semiconductor memories, mass memories of disks and tapes, logic circuits and systems, data entry systems, and distributed storage systems
* New classes of matrix codes, such as error locating codes, spotty byte error control codes, and unequal error control codes, are introduced along with their applications
* A new parallel decoding algorithm of the burst error control codes is demonstrated
In addition to the treatment of matrix codes, the author provides readers with a general overview of the latest developments and advances in the field of code design. Examples, figures, and exercises are fully provided in each chapter to illustrate concepts and engage the reader in designing actual code and solving real problems. The matrix codes presented with practical parameter settings will be very useful for practicing engineers and researchers. References lead to additional material so readers can explore advanced topics in depth.
Engineers, researchers, and designers involved in dependable system design and code design research will find the unique focus and perspective of this practical guide and reference helpful in finding solutions to many key industry problems. It also can serve as a coursebook for graduate and advanced undergraduate students.
Table of Contents
Preface.
1. Introduction.
1.1 Faults and Failures.
1.2 Error Models.
1.3 Error Recovery Techniques for Dependable Systems.
1.4 Code Design Process for Dependable Systems.
References.
2. Mathematical Background and Matrix Codes.
2.1 Introduction to Algebra.
2.2 Linear Codes.
2.3 Basic Matrix Codes.
Exercises.
References.
3. Design Techniques for Matrix Codes.
3.1 Minimum-Weight & Equal-Weight-Row Codes.
3.2 Odd-Weight-Column Codes.
3.3 Even-Weight-Row Codes.
3.4 Odd-Weight-Row Codes.
3.5 Rotational Codes.
Exercises.
References.
4. Codes for High-Speed Memories I: Bit Error Control Codes.
4.1 Modified Hamming SEC-DED Codes.
4.2 Modified Double-Bit Error Correcting BCH Codes.
4.3 On-Chip ECCs.
Exercises.
References.
5. Codes for High-Speed Memories II: Byte Error Control Codes.
5.1 Single-Byte Error Correcting (SbEC) Codes.
5.2 Single-Byte Error Correcting and Double-Byte Error Detecting (SbEC-DbED) Codes.
5.3 Single-Byte Error Correcting and Single p-Byte within a Block Error Detecting (SbEC-Spb=BED) Codes.
Exercises.
References.
6. Codes for High-Speed Memories III: Bit / Byte Error Control Codes.
6.1 Single-Byte / Burst Error Detecting SEC-DED Codes.
6.2 Single-Byte Error Correcting and Double-Bit Error Detecting (SbEC-DED) Codes.
6.3 Single-Byte Error Correcting and Double-Bit Error Correcting (SbEC-DEC) Codes.
6.4 Single-Byte Error Correcting and Single-Byte Plus Single-Bit Error Detecting (SbEC-(SbþS)ED) Codes.
Exercises.
References.
7. Codes for High-Speed Memories IV: Spotty Byte Error Control Codes.
7.1 Spotty Byte Errors.
7.2 Single Spotty Byte Error Correcting (St=bEC) Codes.
7.3 Single Spotty Byte Error Correcting and Single-Byte Error Detecting (St=bEC-SbED) Codes.
7.4 Single Spotty Byte Error Correcting and Double Spotty Byte Error Detecting (St=bEC-Dt=bED) Codes.
7.5 A General Class of Spotty Byte Error Control Codes.
Exercises.
References.
8. Paralled Decoding for Burst / Byte Error Control Codes.
8.1 Parallel Decoding Burst Error Control Codes.
8.2 Parallel Decoding Cyclic Burst Error Correcting Codes.
8.3 Transient Behavior of Parallel Encoder / Decoder Circuits of Error Control Codes.
Exercises.
References.
9. Codes for Error Location: Error Locating Codes.
9.1 Error Location of Faulty Packages and Faulty Chips.
9.2 Block Error Locating (Sb=pbEL) Codes.
9.3 Single-Bit Error Correcting and Single-Block Error Locating (SEC-Sb=pbEL) Codes.
9.4 Single-Bit Error Correcting and Single-Byte Error Locating (SEC-Se=bEL) Codes.
9.5 Burst Error Locating Codes.
9.6 Code Conditions for Error Locating Codes.
10. Codes for Unequal Error Control / Protection (UEC / UEP).
10.1 Error Models for UEC Codes and UEP Codes.
10.2 Fixed-Byte Error Control UEC Codes.
10.3 Burst Error Control UEC / UEP Codes.
10.4 Application of the UEC / UEP Codes.
Exercises.
References.
11. Codes for Mass Memories.
11.1 Tape Memory Codes.
11.2 Magnetic Disk Memory Codes.
11.3 Optical Disk Memory Codes.
Exercises.
References.
12. Coding for Logic and System Design.
12.1 Self-checking Concept.
12.2 Self-testing Checkers.
12.3 Self-checking ALU.
12.4 Self-checking Design for Computer Systems.
Exercises.
References.
13. Codes for Data Entry Systems.
13.1 M-Ary Asymmetric Errors in Data Entry Systems.
13.2 M-Ary Asymmetric Symbol Error Correcting Codes.
13.3 Nonsystematic M-Ary Asymmetric Error Correcting Codes with Deletion / Insertion / Adjacent-Symbol-Transposition Error Correction Capabilities.
13.4 Codes for Two-Dimentional Matrix Symbols.
Exercises.
References.
14. Codes for Multiple / Distributed Storage Systems.
14.1 MDS Array Codes Tolerating Multiple-Disk Failures.
14.2 Codes for Distributed Storage Systems.
Exercises.
References.
Index.
商品描述(中文翻譯)
**描述**
理論與實用工具以掌握矩陣碼設計策略與技術
錯誤更正與檢測碼對於提高系統可靠性至關重要，並已廣泛應用於計算機系統和通信系統。編碼理論主要是使用碼生成多項式進行研究，因此這些碼有時被稱為多項式碼。另一方面，本書中由奇偶檢查矩陣設計的碼被稱為矩陣碼。本書及時地聚焦於矩陣碼的設計理論及其在提高系統可靠性方面的實際應用。正如作者有效地展示的，矩陣碼比多項式碼靈活得多，因為它們能夠表達各種類型的碼功能。
與其他編碼理論出版物相比，本書不會讓讀者承擔不必要的多項式代數負擔，而是專注於理解和充分利用矩陣碼結構和設計所需的基本要素。讀者將獲得一整套理論和實用工具，以掌握矩陣碼設計策略與技術的細節：
* 碼設計與實際應用相關，例如高速半導體記憶體、磁碟和磁帶的大容量記憶體、邏輯電路和系統、數據輸入系統以及分散式存儲系統
* 介紹新類別的矩陣碼，如錯誤定位碼、斷斷續續的位元錯誤控制碼和不等錯誤控制碼及其應用
* 演示一種新的突發錯誤控制碼的平行解碼算法
除了對矩陣碼的處理外，作者還為讀者提供了有關編碼設計領域最新發展和進展的一般概述。每章都提供了示例、圖形和練習，以說明概念並吸引讀者設計實際碼和解決實際問題。以實際參數設置呈現的矩陣碼將對實踐中的工程師和研究人員非常有用。參考文獻引導讀者探索進階主題。
參與可靠系統設計和編碼設計研究的工程師、研究人員和設計師將發現這本實用指南和參考書的獨特焦點和視角對於解決許多關鍵行業問題非常有幫助。它也可以作為研究生和高年級本科生的課本。
**目錄**
前言。
1. 介紹。
1.1 故障與失效。
1.2 錯誤模型。
1.3 可靠系統的錯誤恢復技術。
1.4 可靠系統的碼設計過程。
參考文獻。
2. 數學背景與矩陣碼。
2.1 代數簡介。
2.2 線性碼。
2.3 基本矩陣碼。
練習。
參考文獻。
3. 矩陣碼的設計技術。
3.1 最小權重與等權重行碼。
3.2 奇權重列碼。
3.3 偶權重行碼。
3.4 奇權重行碼。
3.5 旋轉碼。
練習。
參考文獻。
4. 高速記憶體的碼 I：位元錯誤控制碼。
4.1 修改的 Hamming SEC-DED 碼。
4.2 修改的雙位元錯誤更正 BCH 碼。
4.3 片上 ECC。
練習。
參考文獻。
5. 高速記憶體的碼 II：位元組錯誤控制碼。
5.1 單位元組錯誤更正 (SbEC) 碼。
5.2 單位元組錯誤更正和雙位元組錯誤檢測 (SbEC-DbED) 碼。
5.3 單位元組錯誤更正和單 p-位元組內的區塊錯誤檢測 (SbEC-Spb=BED) 碼。
練習。
參考文獻。
6. 高速記憶體的碼 III：位元/位元組錯誤控制碼。
6.1 單位元組/突發錯誤檢測 SEC-DED 碼。
6.2 單位元組錯誤更正和雙位元錯誤檢測 (SbEC-DED) 碼。
6.3 單位元組錯誤更正和雙位元錯誤更正 (SbEC-DEC) 碼。
6.4 單位元組錯誤更正和單位元組加單位元錯誤檢測 (SbEC-(Sb∧S)ED) 碼。
練習。
參考文獻。
7. 高速記憶體的碼 IV：斷斷續續的位元組錯誤控制碼。
7.1 斷斷續續的位元組錯誤。
7.2 單斷斷續位元組錯誤更正 (St=bEC) 碼。
7.3 單斷斷續位元組錯誤更正和單位元組錯誤檢測 (St=bEC-SbED) 碼。
7.4 單斷斷續位元組錯誤更正和雙斷斷續位元組錯誤檢測 (St=bEC-Dt=bED) 碼。
7.5 一般類別的斷斷續位元組錯誤控制碼。
練習。
參考文獻。
8. 突發/位元組錯誤控制碼的平行解碼。
8.1 平行解碼突發錯誤控制碼。
8.2 平行解碼循環突發錯誤更正碼。
8.3 錯誤控制碼的平行編碼器/解碼器電路的瞬態行為。
練習。
參考文獻。
9. 錯誤定位碼：錯誤定位碼。
9.1 故障包和故障晶片的錯誤定位。
9.2 區塊錯誤定位 (Sb=pbEL) 碼。
9.3 單位元錯誤更正和單區塊錯誤定位 (SEC-Sb=pbEL) 碼。
9.4 單位元錯誤更正和單位元組錯誤定位 (SEC-Se=bEL) 碼。
9.5 突發錯誤定位碼。
9.6 錯誤定位碼的碼條件。
參考文獻。
10. 不等錯誤控制/保護 (UEC / UEP) 的碼。
10.1 UEC 碼和 UEP 碼的錯誤模型。
10.2 固定位元組錯誤控制 UEC 碼。
10.3 突發錯誤控制 UEC / UEP 碼。
10.4 UEC / UEP 碼的應用。
練習。
參考文獻。
11. 大容量記憶體的碼。
11.1 磁帶記憶體碼。
11.2 磁碟記憶體碼。
11.3 光碟記憶體碼。
練習。
參考文獻。
12. 邏輯與系統設計的編碼。
12.1 自檢概念。
12.2 自測試檢查器。
12.3 自檢 ALU。
12.4 計算機系統的自檢設計。
練習。
參考文獻。
13. 數據輸入系統的碼。
13.1 數據輸入系統中的 M-元不對稱錯誤。
13.2 M-元不對稱符號錯誤更正碼。
13.3 具有刪除/插入/相鄰符號置換錯誤更正能力的非系統 M-元不對稱錯誤更正碼。
13.4 二維矩陣符號的碼。
練習。
參考文獻。
14. 多重/分散式存儲系統的碼。
14.1 容忍多磁碟故障的 MDS 陣列碼。
14.2 分散式存儲系統的碼。
練習。
參考文獻。
索引。
