Tradeoffs and Optimization in Analog CMOS Design (Hardcover)
暫譯: 類比 CMOS 設計中的權衡與優化 (精裝版)

David Binkley

  • 出版商: Wiley
  • 出版日期: 2008-05-01
  • 售價: $5,590
  • 貴賓價: 9.5$5,311
  • 語言: 英文
  • 頁數: 632
  • 裝訂: Hardcover
  • ISBN: 0470031360
  • ISBN-13: 9780470031360
  • 相關分類: CMOS
  • 海外代購書籍(需單獨結帳)

買這商品的人也買了...

相關主題

商品描述

Analog CMOS integrated circuits are in widespread use for communications, entertainment, multimedia, biomedical, and many other applications that interface with the physical world. Although analog CMOS design is greatly complicated by the design choices of drain current, channel width, and channel length present for every MOS device in a circuit, these design choices afford significant opportunities for optimizing circuit performance.

This book addresses tradeoffs and optimization of device and circuit performance for selections of the drain current, inversion coefficient, and channel length, where channel width is implicitly considered. The inversion coefficient is used as a technology independent measure of MOS inversion that permits design freely in weak, moderate, and strong inversion. 

This book details the significant performance tradeoffs available in analog CMOS design and guides the designer towards optimum design by describing:

  • An interpretation of MOS modeling for the analog designer, motivated by the EKV MOS model, using tabulated hand expressions and figures that give performance and tradeoffs for the design choices of drain current, inversion coefficient, and channel length; performance includes effective gate-source bias and drain-source saturation voltages, transconductance efficiency, transconductance distortion, normalized drain-source conductance, capacitances, gain and bandwidth measures, thermal and flicker noise, mismatch, and gate and drain leakage current
  • Measured data that validates the inclusion of important small-geometry effects like velocity saturation, vertical-field mobility reduction, drain-induced barrier lowering, and inversion-level increases in gate-referred, flicker noise voltage
  • In-depth treatment of moderate inversion, which offers low bias compliance voltages, high transconductance efficiency, and good immunity to velocity saturation effects for circuits designed in modern, low-voltage processes
  • Fabricated design examples that include operational transconductance amplifiers optimized for various tradeoffs in DC and AC performance, and micropower, low-noise preamplifiers optimized for minimum thermal and flicker noise
  • A design spreadsheet, available at the book web site, that facilitates rapid, optimum design of MOS devices and circuits 

Tradeoffs and Optimization in Analog CMOS Design is the first book dedicated to this important topic. It will help practicing analog circuit designers and advanced students of electrical engineering build design intuition, rapidly optimize circuit performance during initial design, and minimize trial-and-error circuit simulations. 

商品描述(中文翻譯)

類比 CMOS 集成電路廣泛應用於通訊、娛樂、多媒體、生物醫學及許多其他與物理世界互動的應用。儘管類比 CMOS 設計因每個電路中 MOS 器件的漏電流、通道寬度和通道長度的設計選擇而變得相當複雜,但這些設計選擇為優化電路性能提供了重要的機會。

本書探討了漏電流、反轉係數和通道長度的選擇所帶來的器件和電路性能的權衡與優化,其中通道寬度被隱含考慮。反轉係數作為一種與技術無關的 MOS 反轉測量,允許在弱、中等和強反轉中自由設計。

本書詳細說明了類比 CMOS 設計中可用的顯著性能權衡,並通過以下內容指導設計師朝向最佳設計:

- 對於類比設計師的 MOS 建模解釋,受到 EKV MOS 模型的啟發,使用表格化的手動表達式和圖形,提供漏電流、反轉係數和通道長度的設計選擇的性能和權衡;性能包括有效的閘源偏壓和漏源飽和電壓、跨導效率、跨導失真、標準化的漏源導納、電容、增益和帶寬測量、熱噪聲和閃爍噪聲、不匹配,以及閘極和漏極漏電流。
- 驗證重要小幾何效應的測量數據,如速度飽和、垂直場移動性降低、漏電引起的障礙降低,以及閘極參考的閃爍噪聲電壓的反轉水平增加。
- 對中等反轉的深入探討,提供低偏壓合規電壓、高跨導效率,以及對速度飽和效應的良好免疫力,適用於在現代低電壓工藝中設計的電路。
- 包含針對直流和交流性能的各種權衡優化的運算跨導放大器的製作設計範例,以及針對最小熱噪聲和閃爍噪聲優化的微功率低噪聲前置放大器。
- 一本設計電子表格,提供於本書網站,便於快速、最佳的 MOS 器件和電路設計。

類比 CMOS 設計中的權衡與優化 是第一本專注於這一重要主題的書籍。它將幫助實踐中的類比電路設計師和電機工程的高級學生建立設計直覺,快速優化初始設計中的電路性能,並最小化試錯電路模擬。