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商品描述
Description
This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by which sub-threshold and gate oxide leakage currents are generated. The authors present a comprehensive review of state-of-the-art dynamic, static supply and threshold voltage scaling techniques and discuss the pros and cons of supply and threshold voltage scaling techniques.
Table of Contents
List of Tables.List of Figures.
Preface.
1 Introduction.
1.1 Evolution of Integrated Circuits.
1.2 Outline of the Book.
2 Sources of Power Consumption in CMOS Integrated Circuits.
2.1 Dynamic Switching Power.
2.2 Leakage Power.
2.3 Short-Circuit Power.
2.4 Static DC Power.
3 Supply and Threshold Voltage Scaling Techniques.
3.1 Dynamic Supply Voltage Scaling.
3.2 Multiple Supply Voltage CMOS.
3.3 Threshold Voltage Scaling.
3.4 Multiple Supply and Threshold Voltage CMOS.
3.5 Dynamic Supply and Threshold Voltage Scaling.
3.6 Circuits with Multiple Voltage and Clock Domains.
3.7 Chapter Summary.
4 Low Voltage Power Supplies.
4.1 Linear DC-DC Converters.
4.2 Switched-Capacitor DC-DC Converters.
4.3 Switching DC-DC Converters.
4.4 Chapter Summary.
5 Analysis of Buck Converters for On-Chip Integration with a Dual Supply Voltage Microprocessor.
5.1 Circuit Model of a Buck Converter.
5.2 Efficiency Analysis of a Buck Converter.
5.3 Simulation Results.
5.4 Chapter Summary.
6 Low Voltage Swing Monolithic DC-DC Conversion.
6.1 Circuit Model of a Low Voltage Swing Buck Converter.
6.2 Low Voltage Swing Buck Converter Analysis.
6.3 Chapter Summary.
7 High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.
7.1 Cascode Bridge Circuits.
7.2 High Input Voltage Monolithic Switching DC-DC Converters.
7.3 Chapter Summary.
8 Signal Transfer in Integrated Circuits with Multiple Supply Voltages.
8.1 A High Speed and Low Power Voltage Interface Circuit.
8.2 Voltage Interface Circuit Simulation Results.
8.3 Experimental Results.
8.4 Chapter Summary.
9 Domino Logic with Variable Threshold Voltage Keeper.
9.1 Standard Domino Logic Circuits.
9.2 Domino Logic with Variable Threshold Voltage Keeper.
9.3 Simulation Results.
9.4 Domino Logic with Forward and Reverse Body Biased Keeper.
9.5 Chapter Summary.
10 Subthreshold Leakage Current Characteristics of Dynamic Circuits.
10.1 State Dependent Subthreshold Leakage Current Characteristics.
10.2 Noise Immunity.
10.3 Power and Delay Characteristics in the Active Mode.
10.4 Dual Threshold Voltage CMOS Technology.
10.5 Chapter Summary.
11Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Standby Leakage Current.
11.1 Previously Published Sleep Mode Circuit Techniques.
11.2 Dual Threshold Voltage Domino Logic Employing Sleep Switches.
11.3 Simulation Results.
11.4 Noise Immunity Compensation.
11.5 Chapter Summary.
12 Conclusions.
Bibliography.
Index.
About the Authors.
商品描述(中文翻譯)
**描述**
本書深入探討基於多重供應電壓和閾值電壓的各種功率降低和速度提升技術。將詳細討論CMOS電路中功耗的來源，並主要集中於識別亞閾值和閘氧化物漏電流產生的機制。作者提供了對最先進的動態、靜態供應電壓和閾值電壓縮放技術的全面回顧，並討論了供應電壓和閾值電壓縮放技術的優缺點。
**目錄**
**表格清單**
**圖形清單**
**前言**
**1 引言**
1.1 集成電路的演變
1.2 本書大綱
**2 CMOS集成電路中的功耗來源**
2.1 動態開關功率
2.2 漏電功率
2.3 短路功率
2.4 靜態直流功率
**3 供應電壓和閾值電壓縮放技術**
3.1 動態供應電壓縮放
3.2 多重供應電壓CMOS
3.3 閾值電壓縮放
3.4 多重供應和閾值電壓CMOS
3.5 動態供應和閾值電壓縮放
3.6 具有多重電壓和時鐘域的電路
3.7 本章小結
**4 低電壓電源**
4.1 線性DC-DC轉換器
4.2 開關電容DC-DC轉換器
4.3 開關DC-DC轉換器
4.4 本章小結
**5 針對雙供應電壓微處理器的片上集成降壓轉換器分析**
5.1 降壓轉換器的電路模型
5.2 降壓轉換器的效率分析
5.3 模擬結果
5.4 本章小結
**6 低電壓擺幅單片DC-DC轉換**
6.1 低電壓擺幅降壓轉換器的電路模型
6.2 低電壓擺幅降壓轉換器分析
6.3 本章小結
**7 用於低電壓CMOS工藝集成的高輸入電壓降壓DC-DC轉換器**
7.1 串聯橋電路
7.2 高輸入電壓單片開關DC-DC轉換器
7.3 本章小結
**8 具有多重供應電壓的集成電路中的信號傳輸**
8.1 高速低功耗電壓介面電路
8.2 電壓介面電路模擬結果
8.3 實驗結果
8.4 本章小結
**9 具有可變閾值電壓保持器的多米諾邏輯**
9.1 標準多米諾邏輯電路
9.2 具有可變閾值電壓保持器的多米諾邏輯
9.3 模擬結果
9.4 具有正向和反向體偏壓保持器的多米諾邏輯
9.5 本章小結
**10 動態電路的亞閾值漏電流特性**
10.1 狀態依賴的亞閾值漏電流特性
10.2 噪聲免疫性
10.3 主動模式下的功率和延遲特性
10.4 雙閾值電壓CMOS技術
10.5 本章小結
**11 具有降低待機漏電流的睡眠開關雙閾值電壓多米諾邏輯**
11.1 先前發表的睡眠模式電路技術
11.2 採用睡眠開關的雙閾值電壓多米諾邏輯
11.3 模擬結果
11.4 噪聲免疫補償
11.5 本章小結
**12 結論**
**參考文獻**
**索引**
**關於作者**
