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商品描述
This volume covers digital design techniques, exercises and applications. The book discusses digital design and implementation in the context of VLSI and embedded system design. It covers basic digital design techniques to high speed design techniques. The contents also cover performance improvement, optimization concepts and design case studies. It includes pedagogical features such as design examples and illustrations. This book will be a useful guide for hardware engineers, logic design engineers, professionals and hobbyists looking to learn and use the digital design to develop VLSI based algorithms, architectures and products.
商品描述(中文翻譯)
本書涵蓋數位設計技術、練習和應用。書中討論了在 VLSI 和嵌入式系統設計背景下的數位設計與實現。內容從基本的數位設計技術到高速設計技術都有涉及。還包括性能提升、優化概念和設計案例研究。書中包含了教學特徵，如設計範例和插圖。本書將成為硬體工程師、邏輯設計工程師、專業人士及愛好者學習和使用數位設計以開發基於 VLSI 的演算法、架構和產品的有用指南。
作者簡介
Vaibbhav Taraate is Entrepreneur and Mentor at "1 Rupee S T". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from Indian Institute of Technology (IIT) Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.
作者簡介(中文翻譯)
Vaibbhav Taraate 是「1 Rupee S T」的企業家和導師。他擁有來自科爾哈普爾的希瓦吉大學（Shivaji University）的電子工程學士學位（B.E.），並因在所有工程學科中名列第一而獲得金牌。他於1999年在印度理工學院孟買分校（IIT Bombay）完成航空航天控制與指導的碩士學位（M.Tech.）。他在半定制ASIC和FPGA設計方面擁有超過18年的經驗，主要使用HDL語言如Verilog和VHDL。他曾擔任幾家跨國公司的顧問、高級設計工程師和技術經理。他的專業領域包括使用VHDL的RTL設計、使用Verilog的RTL設計、複雜的基於FPGA的設計、低功耗設計、綜合/優化、靜態時序分析、使用微處理器的系統設計、高速VLSI設計以及複雜SOC的架構設計。
