High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
暫譯: 多處理器系統單晶片的高階可靠性估算與探索（計算機架構與設計方法論）

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.