融合數字電路與存內計算的高能效神經網絡處理器（英文版）
岳金山
- 出版商: 清華大學
- 出版日期: 2024-08-01
- 定價: $534
- 售價: 8.5 折 $454
- 語言: 簡體中文
- ISBN: 7302656002
- ISBN-13: 9787302656005
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英文 English
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目錄大綱
Contents
1 Introduction 1
1.1 Research Background and Significance 1
1.1.1 Development Trends of Neural Network 1
1.1.2 Requirements of NN Processor 2
1.1.3 Energy-Efficient NN Processors 4
1.2 Summary of the Research Work 6
1.2.1 Overall Framework of the Research Work 6
1.2.2 Main Contributions of This Book 7
1.3 Overall Structure of This Book 8
References 9
2 Basics and Research Status of Neural Network Processors 13
2.1 Basics of Neural Network Algorithms 13
2.2 Basics of Neural Network Processors 16
2.3 Research Status of Digital-Circuits-Based NN Processors 18
2.3.1 Data Reuse 18
2.3.2 Low-Bit Quantization 20
2.3.3 NN Model Compression and Sparsity 21
2.3.4 Summary of Digital-Circuits-Based NN Processors 23
2.4 Research Status of CIM NN Processors 23
2.4.1 CIM Principle 24
2.4.2 CIM Devices 25
2.4.3 CIM Circuits 26
2.4.4 CIM Macro 27
2.4.5 Summary of CIM NN Processors 28
2.5 Summary of This Chapter 28
References 29
3 Energy-Efficient NN Processor by Optimizing Data Reuse for Specific Convolutional Kernels 33
3.1 Introduction 33
3.2 Previous Data Reuse Methods and the Constraints 33
3.3 The KOP3 Processor Optimized for Specific Convolutional Kernels 35
3.4 Processing Array Optimized for Specific Convolutional Kernels 36
3.5 Local Memory Cyclic Access Architecture and Scheduling Strategy 39
3.6 Module-Level Parallel Instruction Set and the Control Circuits 40
3.7 Experimental Results 41
3.8 Conclusion 44
References 45
4 Optimized Neural Network Processor Based on Frequency-Domain Compression Algorithm 47
4.1 Introduction 47
4.2 The Limitations of Irregular Sparse Optimization and CirCNN Frequency-Domain Compression Algorithm 47
4.3 Frequency-Domain NN Processor STICKER-T 50
4.4 Global-Parallel Bit-Serial FFT Circuits 52
4.5 Frequency-Domain 2D Data-Reuse MAC Array 55
4.6 Small-Area Low-Power Block-Wise TRAM 59
4.7 Chip Measurement Results and Comparison 62
4.8 Summary of This Chapter 69
References 69
5 Digital Circuits and CIM Integrated NN Processor 71
5.1 Introduction 71
5.2 The Advantage of CIM Over Pure Digital Circuits 71
5.3 Design Challenges for System-Level CIM Chips 74
5.4 Sparse CIM Processor STICKER-IM 78
5.5 Structural Block-Wise Weight Sparsity and Dynamic Activation Sparsity 79
5.6 Flexible Mapping and Scheduling and Intra/Inter-Macro Data Reuse 81
5.7 Energy-Efficient CIM Macro with Dynamic ADC Power-Off 85
5.8 Chip Measurement Results and Comparison 88
5.9 Summary of This Chapter 92
References 93
6 A “Digital+CIM” Processor Supporting Large-Scale NN Models 95
6.1 Introduction 95
6.2 The Challenges of System-Level CIM Chips to Support Large-Scale NN Models 95
6.3 “Digital+CIM” NN Processor STICKER-IM2 97
6.4 Set-Associate Block-Wise Sparse Zero-Skipping Circuits 98
6.5 Ping-Pong CIM and Weight Update Architecture 100
6.6 Ping-Pong CIM Macro with Dynamic ADC Precision 103
6.7 Chip Measurement Results and Comparison 104
6.8 Summary of This Chapter 112
References 112
7 Summary and Prospect 115
7.1 Summary of This Book 115
7.2 Prospect of This Book 117
