A Novel Methodology for High Speed Board Design: Prevent Crosstalk, Improve Signal & Power Integrity and Reduce EM Emission (Paperback)
暫譯: 高效能電路板設計的新方法:防止串擾、改善信號與電源完整性及降低電磁輻射

Thiagarajan Kandasamy

  • 出版商: LAP LAMBERT
  • 出版日期: 2012-07-16
  • 售價: $2,130
  • 貴賓價: 9.5$2,024
  • 語言: 英文
  • 頁數: 112
  • 裝訂: Paperback
  • ISBN: 3659184365
  • ISBN-13: 9783659184369
  • 無法訂購

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商品描述

Current high-speed designs demand a board designer’s extensive knowledge of the issues like transmission line effect, EMI, and crosstalk. Modern PCB design concerned with board material, signal and power stacking, connectors, cables, vias, and trace dimensions. With such designs, the complexity of PCB design increases with the aspects of SI which originate noise and instability. Crosstalk is a major noise that interferes with SI. The noise voltage in the reference or ground of a PCB is often the cause of unwanted radiated emission. Power supply planes attribute to the noise voltage. A Gigabit Ethernet design is developed to analyze various issues on PCB designs like Crosstalk, SI & PI, EMI and Thermal variations. Techniques are investigated to reduce the radiated EM fields, improve power delivery system of the design and eliminate the crosstalk related to routing the high speed signals. SI analysis & thermal analysis help to improve design characteristics. EMI results are within the limits of FCC-CLASS B/ VCCI-CLASS B standards with crosstalk within the limit of 100mV. The design is developed to achieve DFA/DFM/DFT for the manufacturing process of high speed & high dense PCB.

商品描述(中文翻譯)

當前的高速設計要求電路板設計師對傳輸線效應、電磁干擾 (EMI) 和串擾等問題有廣泛的了解。現代的印刷電路板 (PCB) 設計涉及板材、信號和電源堆疊、連接器、電纜、通孔和走線尺寸等方面。隨著這些設計的進行,PCB 設計的複雜性隨著源自噪聲和不穩定性的信號完整性 (SI) 問題而增加。串擾是干擾信號完整性的主要噪聲。PCB 的參考或接地中的噪聲電壓通常是導致不必要輻射發射的原因。電源平面會影響噪聲電壓。開發了一個千兆以太網設計,以分析 PCB 設計中的各種問題,如串擾、信號完整性 (SI) 和電源完整性 (PI)、EMI 以及熱變化。研究了減少輻射電磁場、改善設計的電源傳遞系統以及消除與高速信號路由相關的串擾的技術。信號完整性分析和熱分析有助於改善設計特性。EMI 的結果在 FCC-CLASS B/VCCI-CLASS B 標準的限制範圍內,串擾在 100mV 的限制內。該設計旨在實現高速度和高密度 PCB 的製造過程中的設計可製造性 (DFA)、設計可製造性 (DFM) 和設計可測試性 (DFT)。