System Level Design from HW/SW to Memory for Embedded Systems: 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, ... in Information and Communication Technology)
暫譯: 嵌入式系統的系統級設計：第五屆IFIP TC 10國際嵌入式系統研討會（IESS 2015），福斯杜伊瓜蘇，...在資訊與通信技術中的應用
相關主題
商品描述
This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015.
The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.
商品描述(中文翻譯)
本書是2015年11月在巴西伊瓜蘇舉行的第五屆IFIP TC 10國際嵌入式系統研討會（IESS 2015）的經過審稿的會議論文集。
所呈現的18篇完整修訂論文是從25篇投稿中仔細審核和選出的。這些論文廣泛討論了嵌入式系統和網路物理系統的設計、分析和驗證，包括設計方法論、驗證、性能分析和即時系統設計。論文組織在以下主題部分：網路物理系統、系統級設計；多核心/多核系統設計；記憶體系統設計；以及嵌入式硬體/軟體設計與應用。
